[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Enable cr50 TPM interrupt

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16661

-gerrit

commit a5f5f5778fc7efacf8ea1565263fdda04f2b9084
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 19 17:24:55 2016 -0700

    mainboard/google/reef: Enable cr50 TPM interrupt
    
    Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
    verstage.  The interrupt is left in APIC mode as the GPE is
    still latched when the GPIO is pulled low.
    
    BUG=chrome-os-partner:53336
    
    Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/reef/Kconfig                   | 4 ++++
 src/mainboard/google/reef/variants/baseboard/gpio.c | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 0013ffd..1ba43a5 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select I2C_TPM
+	select I2C_TPM_CR50
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
 	select TPM2
@@ -24,6 +25,9 @@ config DRIVER_TPM_I2C_BUS
 config DRIVER_TPM_I2C_ADDR
 	hex "0x50"
 
+config DRIVER_TPM_I2C_IRQ
+	int "60" # GPE0_DW1_28
+
 config CHROMEOS
 	select LID_SWITCH if BASEBOARD_REEF_LAPTOP
 
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 7d74140c..976a504 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -353,6 +353,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* I2C2 - TPM  */
 	PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
 	PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
+	PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
 	/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
 	PAD_CFG_GPO(GPIO_122, 0, DEEP),		 /* SIO_SPI_2_RXD */
 };