[coreboot-gerrit] Patch set updated for coreboot: src/mainboard/getac - kontron: Add space around operators
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Tue Sep 20 20:31:37 CEST 2016
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16640
-gerrit
commit 1538d890c414a10389d90a943cb9695a8f572436
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Sep 19 09:46:33 2016 -0600
src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/getac/p470/irq_tables.c | 40 +++++++++++-----------
src/mainboard/getac/p470/romstage.c | 4 +--
src/mainboard/gigabyte/ga-6bxc/irq_tables.c | 14 ++++----
src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 8 ++---
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 8 ++---
src/mainboard/gigabyte/m57sli/fanctl.c | 2 +-
src/mainboard/gigabyte/m57sli/mptable.c | 14 ++++----
src/mainboard/gigabyte/m57sli/romstage.c | 8 ++---
src/mainboard/gigabyte/ma785gm/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gm/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +-
src/mainboard/gigabyte/ma78gm/mptable.c | 2 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 2 +-
src/mainboard/google/butterfly/chromeos.c | 2 +-
src/mainboard/google/butterfly/hda_verb.c | 12 +++----
src/mainboard/google/butterfly/mainboard.c | 2 +-
src/mainboard/google/cyan/spd/spd.c | 6 ++--
src/mainboard/google/falco/Makefile.inc | 16 ++++-----
src/mainboard/google/falco/gma.c | 2 +-
src/mainboard/google/falco/i915io.c | 4 +--
src/mainboard/google/guado/lan.c | 2 +-
src/mainboard/google/guado/romstage.c | 4 +--
src/mainboard/google/guado/smihandler.c | 8 ++---
src/mainboard/google/jecht/lan.c | 2 +-
src/mainboard/google/link/i915.c | 26 +++++++--------
src/mainboard/google/link/i915io.c | 16 ++++-----
src/mainboard/google/link/i915io.h | 2 +-
src/mainboard/google/ninja/lan.c | 2 +-
src/mainboard/google/panther/lan.c | 2 +-
src/mainboard/google/peach_pit/mainboard.c | 6 ++--
src/mainboard/google/peppy/gma.c | 2 +-
src/mainboard/google/rikku/lan.c | 2 +-
src/mainboard/google/rikku/romstage.c | 4 +--
src/mainboard/google/rikku/smihandler.c | 8 ++---
src/mainboard/google/stout/mainboard.c | 2 +-
src/mainboard/google/tidus/lan.c | 2 +-
src/mainboard/google/tidus/led.c | 8 ++---
src/mainboard/hp/dl145_g1/acpi_tables.c | 4 +--
src/mainboard/hp/dl145_g1/fadt.c | 12 +++----
src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 +--
src/mainboard/hp/dl145_g1/irq_tables.c | 2 +-
src/mainboard/hp/dl145_g1/romstage.c | 30 ++++++++---------
src/mainboard/hp/dl145_g3/get_bus_conf.c | 6 ++--
src/mainboard/hp/dl145_g3/irq_tables.c | 42 ++++++++++++------------
src/mainboard/hp/dl145_g3/mptable.c | 38 ++++++++++-----------
src/mainboard/hp/dl145_g3/romstage.c | 22 ++++++-------
src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 6 ++--
src/mainboard/hp/dl165_g6_fam10/mptable.c | 30 ++++++++---------
src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +-
src/mainboard/ibase/mb899/irq_tables.c | 40 +++++++++++-----------
src/mainboard/ibase/mb899/romstage.c | 16 ++++-----
src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +-
src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c | 18 +++++-----
src/mainboard/intel/bayleybay_fsp/romstage.c | 2 +-
src/mainboard/intel/d945gclf/irq_tables.c | 40 +++++++++++-----------
src/mainboard/intel/eagleheights/debug.c | 6 ++--
src/mainboard/intel/littleplains/irq_tables.c | 28 ++++++++--------
src/mainboard/intel/minnowmax/gpio.c | 2 +-
src/mainboard/intel/mohonpeak/irq_tables.c | 28 ++++++++--------
src/mainboard/intel/mtarvon/mptable.c | 26 +++++++--------
src/mainboard/intel/stargo2/gpio.h | 8 ++---
src/mainboard/intel/truxton/mptable.c | 34 +++++++++----------
src/mainboard/intel/wtm2/graphics.c | 2 +-
src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +-
src/mainboard/iwill/dk8_htx/acpi_tables.c | 8 ++---
src/mainboard/iwill/dk8_htx/fadt.c | 8 ++---
src/mainboard/iwill/dk8_htx/irq_tables.c | 2 +-
src/mainboard/iwill/dk8_htx/mptable.c | 42 ++++++++++++------------
src/mainboard/iwill/dk8_htx/romstage.c | 12 +++----
src/mainboard/jetway/j7f2/irq_tables.c | 22 ++++++-------
src/mainboard/jetway/j7f2/romstage.c | 4 +--
src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 4 +--
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 2 +-
src/mainboard/jetway/pa78vm5/mptable.c | 2 +-
src/mainboard/jetway/pa78vm5/romstage.c | 2 +-
src/mainboard/kontron/986lcd-m/irq_tables.c | 40 +++++++++++-----------
src/mainboard/kontron/986lcd-m/romstage.c | 32 +++++++++---------
src/mainboard/kontron/kt690/fadt.c | 6 ++--
src/mainboard/kontron/kt690/mptable.c | 2 +-
src/mainboard/kontron/kt690/romstage.c | 4 +--
82 files changed, 449 insertions(+), 449 deletions(-)
diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c
index 140b73e..06d1492 100644
--- a/src/mainboard/getac/p470/irq_tables.c
+++ b/src/mainboard/getac/p470/irq_tables.c
@@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b0, /* Device */
@@ -29,25 +29,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
- {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
- {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
- {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
- {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
- {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
- {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
- {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
- {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
- {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
- {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
- {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
- {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
- {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
- {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
- {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+ {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+ {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+ {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+ {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+ {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+ {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+ {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+ {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+ {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+ {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+ {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+ {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+ {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+ {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
}
};
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 396a2ec..bbe45ad 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -82,7 +82,7 @@ static void ich7_enable_lpc(void)
{
int lpt_en = 0;
if (read_option(lpt, 0) != 0) {
- lpt_en = 1<<2; // enable LPT
+ lpt_en = 1 << 2; // enable LPT
}
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
@@ -126,7 +126,7 @@ static void early_superio_config(void)
{
device_t dev;
- dev=PNP_DEV(0x4e, 0x00);
+ dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x02, 0x0e); // UART power
diff --git a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c
index bfcca63..3a641d5 100644
--- a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c
+++ b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c
@@ -29,13 +29,13 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x8, /* Checksum */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
- {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
- {0x00,(0x07<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
+ {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
+ {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
+ {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
+ {0x00,(0x07 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
+ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
}
};
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index 8a955e8..a7962f54 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0, sbdn+5, 2, 0x15); // 21
PCI_INT(0, sbdn+8, 0, 0x16); // 22
- for(j=7; j>=2; j--) {
+ for(j = 7; j >= 2; j--) {
if(!bus_sis966[j]) continue;
- for(i=0;i<4;i++) {
+ for(i = 0; i < 4; i++) {
PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
}
}
- for(j=0; j<2; j++)
- for(i=0;i<4;i++) {
+ for(j = 0; j < 2; j++)
+ for(i = 0; i < 4; i++) {
PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 8bc71a9..68cbaad 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -89,11 +89,11 @@ static void sio_setup(void)
pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
+ dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
+ dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
}
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c
index 07a2666..cc0cdca 100644
--- a/src/mainboard/gigabyte/m57sli/fanctl.c
+++ b/src/mainboard/gigabyte/m57sli/fanctl.c
@@ -75,7 +75,7 @@ static const struct {
void init_ec(uint16_t base)
{
int i;
- for (i=0; i<ARRAY_SIZE(sequence); i++) {
+ for (i = 0; i < ARRAY_SIZE(sequence); i++) {
write_index(base, sequence[i].index, sequence[i].value);
}
}
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index e6cb28b..403b969 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -84,9 +84,9 @@ static void *smp_write_config_table(void *v)
/* The PCIe slots, each on its own bus */
k = 1;
- for(i=0; i<4; i++){
- for(j=7; j>1; j--){
- if(k>3) k=0;
+ for(i = 0; i < 4; i++){
+ for(j = 7; j > 1; j--){
+ if(k > 3) k = 0;
PCI_INT(j,0,i, 16+k);
k++;
}
@@ -97,10 +97,10 @@ static void *smp_write_config_table(void *v)
physical PCI slots are j = 7,8
FireWire is j = 10
*/
- k=2;
- for(i=0; i<4; i++){
- for(j=6; j<11; j++){
- if(k>3) k=0;
+ k = 2;
+ for(i = 0; i < 4; i++){
+ for(j = 6; j < 11; j++){
+ if(k > 3) k = 0;
PCI_INT(1,j,i, 16+k);
k++;
}
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b1c849b..f8d12c6 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -80,11 +80,11 @@ static void sio_setup(void)
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
+ dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
+ dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 4c74e4e..3f9d7c7 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index baf49af..06eaa8c 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 4c74e4e..3f9d7c7 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index b8ab282..860b1f1 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 4c74e4e..3f9d7c7 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 43bae3c..9efda6f 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index b25d78e..b2e3356 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -41,7 +41,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
- int lidswitch=0;
+ int lidswitch = 0;
if (!gpio_base)
return;
diff --git a/src/mainboard/google/butterfly/hda_verb.c b/src/mainboard/google/butterfly/hda_verb.c
index caf8b4a..46d3e86 100644
--- a/src/mainboard/google/butterfly/hda_verb.c
+++ b/src/mainboard/google/butterfly/hda_verb.c
@@ -37,32 +37,32 @@ const u32 cim_verb_data[] = {
AZALIA_SUBVENDOR(0x0, 0x103C18F9),
/* NID 0x0A - External Microphone Connector
- * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ * Config = 0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
*/
AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
/* NID 0x0B - Headphone Connector
- * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ * Config = 0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
*/
AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
/* NID 0x0C - Not connected
- * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ * Config = 0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
*/
AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
/* NID 0x0D - Internal Speakers
- * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ * Config = 0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
*/
AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
/* NID 0x0F - Not connected
- * Config=0x40F000F0
+ * Config = 0x40F000F0
*/
AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
/* NID 0x11 - Internal Microphone
- * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ * Config = 0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
*/
AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140),
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index 2c5170d..dd2f7b5 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -225,7 +225,7 @@ static void mainboard_init(device_t dev)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index c2e9e79..6ab0063 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -113,9 +113,9 @@ void mainboard_fill_spd_data(struct pei_data *ps)
/*
* Set SPD and memory configuration:
- * Memory type: 0=DimmInstalled,
- * 1=SolderDownMemory,
- * 2=DimmDisabled
+ * Memory type: 0 = DimmInstalled,
+ * 1 = SolderDownMemory,
+ * 2 = DimmDisabled
*/
if (spd_content != NULL) {
ps->spd_data_ch0 = spd_content;
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index 34de87a..6ea2284 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -25,14 +25,14 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
SPD_BIN = $(obj)/spd.bin
# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000)
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001)
-SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010)
-SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011)
-SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100)
-SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101)
-SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110)
-SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111)
+SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID = 000)
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID = 001)
+SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID = 010)
+SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID = 011)
+SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID = 100)
+SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID = 101)
+SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID = 110)
+SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID = 111)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c
index 986d9c3..c76c50e 100644
--- a/src/mainboard/google/falco/gma.c
+++ b/src/mainboard/google/falco/gma.c
@@ -90,7 +90,7 @@ static void palette(void)
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
- gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ gtt_write(_LGC_PALETTE_A + (i << 2),color);
}
}
diff --git a/src/mainboard/google/falco/i915io.c b/src/mainboard/google/falco/i915io.c
index 0936de9..5f33586 100644
--- a/src/mainboard/google/falco/i915io.c
+++ b/src/mainboard/google/falco/i915io.c
@@ -84,8 +84,8 @@ void runio(struct intel_dp *dp)
gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
- gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
- gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a);
+ gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a);
intel_dp_set_bw(dp);
intel_dp_set_lane_count(dp);
diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c
index 041c3f0..fa292ad 100644
--- a/src/mainboard/google/guado/lan.c
+++ b/src/mainboard/google/guado/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/guado/romstage.c b/src/mainboard/google/guado/romstage.c
index 24acc80..3ae31f0 100644
--- a/src/mainboard/google/guado/romstage.c
+++ b/src/mainboard/google/guado/romstage.c
@@ -57,8 +57,8 @@ void mainboard_pre_console_init(void)
/* Turn On GPIO10.LED */
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
- 0x01 /* output */, 0x01 /* 1=Simple IO function */,
+ 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+ 0x01 /* output */, 0x01 /* 1 = Simple IO function */,
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
}
diff --git a/src/mainboard/google/guado/smihandler.c b/src/mainboard/google/guado/smihandler.c
index d37cc33..0118e6b 100644
--- a/src/mainboard/google/guado/smihandler.c
+++ b/src/mainboard/google/guado/smihandler.c
@@ -62,14 +62,14 @@ void mainboard_smi_sleep(u8 slp_typ)
switch (slp_typ) {
case ACPI_S3:
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x01 /* polarity */, 0x01 /* 1=pullup */,
- 0x01 /* output */, 0x00, /* 0=Alternate function */
+ 0x01 /* polarity */, 0x01 /* 1 = pullup */,
+ 0x01 /* output */, 0x00, /* 0 = Alternate function */
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
case ACPI_S5:
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
- 0x01 /* output */, 0x01 /* 1=Simple IO function */,
+ 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+ 0x01 /* output */, 0x01 /* 1 = Simple IO function */,
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
default:
diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c
index 651c8e6..e76994f 100644
--- a/src/mainboard/google/jecht/lan.c
+++ b/src/mainboard/google/jecht/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 31249a1..6158f53 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -148,7 +148,7 @@ static void palette(void)
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
- io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
+ io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2));
}
}
@@ -277,57 +277,57 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
index = run(0);
printk(BIOS_SPEW, "Run returns %d\n", index);
- auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe;
+ auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14);
- auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0;
+ auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index);
- auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0;
+ auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0;
auxout[1] = 0x01000000;
/* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
auxout[1] = 0x0a840000;
/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
auxout[2] = 0x00000000;
auxout[3] = 0x01000000;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x21000000;
/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
+ auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x22000000;
/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
+ auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index);
- auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
+ auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x00000000;
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c
index 5ebb42d..0f8e0f2 100644
--- a/src/mainboard/google/link/i915io.c
+++ b/src/mainboard/google/link/i915io.c
@@ -116,8 +116,8 @@ struct iodef iodefs[] = {
{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
- {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
- {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
+ {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x00000000, 0},
+ {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
@@ -194,15 +194,15 @@ struct iodef iodefs[] = {
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
- {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
- {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
- {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
+ {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0},
+ {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | 0x40000000, 0},
+ {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
- {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
+ {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
{R, 1, "", 0x145d10, 0x2010040c, 0},
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
@@ -271,8 +271,8 @@ struct iodef iodefs[] = {
{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
- {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
- {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
+ {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
+ {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0 = A,1 = B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
{R, 1, "", _DSPAADDR, 0x00000000, 0},
{W, 1, "", _DSPAADDR, 0x00000000, 0},
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h
index a7e915a..42893ae 100644
--- a/src/mainboard/google/link/i915io.h
+++ b/src/mainboard/google/link/i915io.h
@@ -18,7 +18,7 @@
/* things that are, strangely, not defined anywhere? */
#define PCH_PP_UNLOCK 0xabcd0000
-#define WMx_LP_SR_EN (1<<31)
+#define WMx_LP_SR_EN (1 << 31)
/* Google Link-specific defines */
/* how many 4096-byte pages do we need for the framebuffer?
diff --git a/src/mainboard/google/ninja/lan.c b/src/mainboard/google/ninja/lan.c
index dad8692..cea30e8 100644
--- a/src/mainboard/google/ninja/lan.c
+++ b/src/mainboard/google/ninja/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c
index 202d8d0..91d882f 100644
--- a/src/mainboard/google/panther/lan.c
+++ b/src/mainboard/google/panther/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 4cc72f1..f6e785c 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -138,18 +138,18 @@ static const struct parade_write parade_writes[] = {
{ 0x04, 0x71, 0x2d },
/*
* 2.7G CDR settings
- * NOF=40LSB for HBR CDR setting
+ * NOF = 40LSB for HBR CDR setting
*/
{ 0x04, 0x7d, 0x07 },
{ 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
{ 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
/*
* 1.62G CDR settings
- * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ * [5:2]NOF = 64LSB [1:0]DCO scale is 2/5
*/
{ 0x04, 0xc0, 0x12 },
{ 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
- { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
+ { 0x04, 0xc2, 0x1c }, /* Fbstep = 100% */
{ 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
/*
* RPIO Setting
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
index 8110c8b..f3470a4 100644
--- a/src/mainboard/google/peppy/gma.c
+++ b/src/mainboard/google/peppy/gma.c
@@ -91,7 +91,7 @@ static void palette(void)
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
- gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ gtt_write(_LGC_PALETTE_A + (i << 2),color);
}
}
diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c
index e5676af..6099bc1 100644
--- a/src/mainboard/google/rikku/lan.c
+++ b/src/mainboard/google/rikku/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c
index 5f06ed9..b626bdd 100644
--- a/src/mainboard/google/rikku/romstage.c
+++ b/src/mainboard/google/rikku/romstage.c
@@ -56,8 +56,8 @@ void mainboard_pre_console_init(void)
/* Turn On GPIO10.LED */
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
- 0x01 /* output */, 0x01 /* 1=Simple IO function */,
+ 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+ 0x01 /* output */, 0x01 /* 1 = Simple IO function */,
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
}
diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c
index 4331a1f..4649411 100644
--- a/src/mainboard/google/rikku/smihandler.c
+++ b/src/mainboard/google/rikku/smihandler.c
@@ -61,14 +61,14 @@ void mainboard_smi_sleep(u8 slp_typ)
switch (slp_typ) {
case ACPI_S3:
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x01 /* polarity */, 0x01 /* 1=pullup */,
- 0x01 /* output */, 0x00, /* 0=Alternate function */
+ 0x01 /* polarity */, 0x01 /* 1 = pullup */,
+ 0x01 /* output */, 0x00, /* 0 = Alternate function */
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
case ACPI_S5:
it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */,
- 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */,
- 0x01 /* output */, 0x01 /* 1=Simple IO function */,
+ 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */,
+ 0x01 /* output */, 0x01 /* 1 = Simple IO function */,
SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
default:
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index 4e3839f..ca67759 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -52,7 +52,7 @@ static void mainboard_init(device_t dev)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID,
STOUT_NIC_DEVICE_ID, dev);
diff --git a/src/mainboard/google/tidus/lan.c b/src/mainboard/google/tidus/lan.c
index 7c03f6c..08205cc 100644
--- a/src/mainboard/google/tidus/lan.c
+++ b/src/mainboard/google/tidus/lan.c
@@ -162,7 +162,7 @@ void lan_init(void)
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
- * enable CLKREQ: LAN pci config space 0x81h=01
+ * enable CLKREQ: LAN pci config space 0x81h = 01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
diff --git a/src/mainboard/google/tidus/led.c b/src/mainboard/google/tidus/led.c
index c0bf332..4c605e6 100644
--- a/src/mainboard/google/tidus/led.c
+++ b/src/mainboard/google/tidus/led.c
@@ -27,9 +27,9 @@ void set_power_led(u8 led_pin_map, int state)
1 /* set */,
0x01 /* select */,
state /* polarity: non-inverting */,
- 0x00 /* 0=pulldown */,
+ 0x00 /* 0 = pulldown */,
0x01 /* output */,
- 0x01 /* 1=Simple IO function */,
+ 0x01 /* 1 = Simple IO function */,
led_pin_map,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
@@ -38,9 +38,9 @@ void set_power_led(u8 led_pin_map, int state)
1 /* set */,
0x01 /* select */,
0x01 /* polarity */,
- 0x01 /* 1=pullup */,
+ 0x01 /* 1 = pullup */,
0x01 /* output */,
- 0x00, /* 0=Alternate function */
+ 0x00, /* 0 = Alternate function */
led_pin_map,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
break;
diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
index c85f380..47e0a3a 100644
--- a/src/mainboard/hp/dl145_g1/acpi_tables.c
+++ b/src/mainboard/hp/dl145_g1/acpi_tables.c
@@ -25,7 +25,7 @@
unsigned long acpi_fill_madt(unsigned long current)
{
- unsigned int gsi_base=0x18;
+ unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i;
int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
+ for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index fb0c62b..877cb5b 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -24,13 +24,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"COREBOOT",8);
memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
+ header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
- // 3=Workstation,4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile=0x04;
- fadt->sci_int=9;
+ // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+ fadt->preferred_pm_profile = 0x04;
+ fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
@@ -59,8 +59,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
- fadt->flush_size = 0; // ignored if wbindv=1 in flags
- fadt->flush_stride = 0; // ignored if wbindv=1 in flags
+ fadt->flush_size = 0; // ignored if wbindv = 1 in flags
+ fadt->flush_stride = 0; // ignored if wbindv = 1 in flags
fadt->duty_offset = 1;
fadt->duty_width = 3; // 0 means duty cycle not supported
// _alrm value 0 means RTC alarm feature not supported
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index 9c35814..da02095 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -52,7 +52,7 @@ void get_bus_conf(void)
device_t dev;
int i;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -60,7 +60,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index 4988ea1..597acca 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -74,7 +74,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++;
slot_num++;
//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
pirq_info++;
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 8b5b428..ea0b60c 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -28,12 +28,12 @@ static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
/* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
@@ -53,11 +53,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
- i=2;
+ /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+ i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret!=0) && (i-->0));
+ } while ((ret != 0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
@@ -65,11 +65,11 @@ static inline void change_i2c_mux(unsigned device)
{
int ret, i;
printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
- i=2;
+ i = 2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
- } while ((ret!=0) && (i-->0));
+ } while ((ret != 0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
}
@@ -91,8 +91,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
+#define RC0 ((1 << 1)<<8)
+#define RC1 ((1 << 2)<<8)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* Read FIDVID_STATUS */
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
@@ -173,10 +173,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
int i;
- for(i=0;i<2;i++) {
+ for(i = 0; i < 2; i++) {
activate_spd_rom(&sysinfo->ctrl[i]);
}
- for(i=RC0;i<=RC1;i<<=1) {
+ for(i = RC0; i <= RC1; i<<=1) {
change_i2c_mux(i);
}
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
index 87f065d..d69e224 100644
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c
@@ -68,7 +68,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -78,7 +78,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -125,6 +125,6 @@ void get_bus_conf(void)
apicid_base = get_apicid_base(3);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- for(i=0;i<3;i++)
+ for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
}
diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c
index 3e256b7..2088baf 100644
--- a/src/mainboard/hp/dl145_g3/irq_tables.c
+++ b/src/mainboard/hp/dl145_g3/irq_tables.c
@@ -9,7 +9,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x0, /* Where the interrupt router lies (bus) */
- (0x2<<3)|0x4,
+ (0x2 << 3)|0x4,
0, /* IRQs devoted exclusively to PCI usage */
0, /* Vendor */
0, /* Device */
@@ -20,26 +20,26 @@ static const struct irq_routing_table intel_irq_routing_table = {
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
- {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
- {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
- {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
- {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
- {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
- //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
- {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
- {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
- {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
- {0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
+ {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
+ {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
+ {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
+ {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
+ {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
+ {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
+ //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
+ {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
+ {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
+ {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
+ //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+ {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
+ //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
+ {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
}
};
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 5aeb71d..3a784e7 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2001 Eric W.Biederman<ebiderman at lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman <ebiderman at lnxi.com>
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0;
int i;
struct resource *res;
- for(i=0; i<3; i++) {
+ for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword);
}
// set GEVENT pins to NO OP
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
+ dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword);
}
}
@@ -116,32 +116,32 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//SATA
-/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
-/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
- printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
+/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
+/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
+ printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
//USB
printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa);
//VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7);
//PCIE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe);
//IDE
// outb(0x02, 0xc00); outb(0x0e, 0xc01);
// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
-// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
+// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe);
//onboard Broadcom GbE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4);
@@ -153,7 +153,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
+ dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 12d18cf..1d1195a 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -79,11 +79,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void setup_early_ipmi_serial()
{
unsigned char result;
- char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
- char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
- char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
- char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
- char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
+ char channel_access[]={0x06 << 2,0x40,0x04,0x80,0x05};
+ char serialmodem_conf[]={0x0c << 2,0x10,0x04,0x08,0x00,0x0f};
+ char serial_mux1[]={0x0c << 2,0x12,0x04,0x06};
+ char serial_mux2[]={0x0c << 2,0x12,0x04,0x03};
+ char serial_mux3[]={0x0c << 2,0x12,0x04,0x07};
// earlydbg(0x0d);
//set channel access system only
@@ -91,19 +91,19 @@ static void setup_early_ipmi_serial()
// earlydbg(result);
/*
//Set serial/modem config
- result=ipmi_request(6,serialmodem_conf);
+ result = ipmi_request(6,serialmodem_conf);
earlydbg(result);
//Set serial mux 1
- result=ipmi_request(4,serial_mux1);
+ result = ipmi_request(4,serial_mux1);
earlydbg(result);
//Set serial mux 2
- result=ipmi_request(4,serial_mux2);
+ result = ipmi_request(4,serial_mux2);
earlydbg(result);
//Set serial mux 3
- result=ipmi_request(4,serial_mux3);
+ result = ipmi_request(4,serial_mux3);
earlydbg(result);
*/
// earlydbg(0x0e);
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
}
#endif
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index e323873..68c3881 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done==1) return; //do it only once
+ if(get_bus_conf_done == 1) return; //do it only once
get_bus_conf_done = 1;
@@ -80,7 +80,7 @@ void get_bus_conf(void)
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for(i=0;i<sysconf.hc_possible_num; i++) {
+ for(i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@@ -124,6 +124,6 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
apicid_base = 0x10;
- for(i=0;i<3;i++)
+ for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 395de57..17e42e4 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2001 Eric W.Biederman<ebiderman at lnxi.com>
+ * Copyright (C) 2001 Eric W.Biederman < ebiderman at lnxi.com>
*
* Copyright (C) 2006 AMD
* Written by Yinghai Lu <yinghailu at gmail.com> for AMD.
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
device_t dev = 0;
int i;
struct resource *res;
- for(i=0; i<3; i++) {
+ for(i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
pci_write_config32(dev, 0x64, dword);
}
// set GEVENT pins to NO OP
@@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1<<26);
+ dword |= (1 << 26);
pci_write_config32(dev, 0x64, dword);
}
}
@@ -113,16 +113,16 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
/* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe << 2)|0, m->apicid_bcm5785[0], 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3 << 2)|0, m->apicid_bcm5785[0], 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|0, m->apicid_bcm5785[2], 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2 << 2)|1, m->apicid_bcm5785[2], 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0 << 2)|0, m->apicid_bcm5785[2], 0xa);
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
@@ -132,7 +132,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1<<4); // enable interrupts
+ dword |= (1 << 4); // enable interrupts
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 84e28f7..39cd0e3 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c
index ab1849d..9c8a5cc 100644
--- a/src/mainboard/ibase/mb899/irq_tables.c
+++ b/src/mainboard/ibase/mb899/irq_tables.c
@@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b9, /* Device */
@@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
- {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
- {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
- {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
- {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
- {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
- {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
- {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
- {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
- {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
- {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
- {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
- {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
- {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
- {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
- {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+ {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+ {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+ {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+ {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+ {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+ {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+ {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+ {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+ {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+ {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+ {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+ {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+ {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
+ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+ {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
}
};
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 9d2b90a..3fa339f 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -87,14 +87,14 @@ static void early_superio_config_w83627ehg(void)
pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
- dev=PNP_DEV(0x4e, W83627EHG_SP1);
+ dev = PNP_DEV(0x4e, W83627EHG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_SP2);
+ dev = PNP_DEV(0x4e, W83627EHG_SP2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
@@ -102,7 +102,7 @@ static void early_superio_config_w83627ehg(void)
// pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
+ dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@@ -110,27 +110,27 @@ static void early_superio_config_w83627ehg(void)
//pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
+ dev = PNP_DEV(0x4e, W83627EHG_GPIO2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it
- dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
+ dev = PNP_DEV(0x4e, W83627EHG_GPIO3);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
- dev=PNP_DEV(0x4e, W83627EHG_FDC);
+ dev = PNP_DEV(0x4e, W83627EHG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627EHG_PP);
+ dev = PNP_DEV(0x4e, W83627EHG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
/* Enable HWM */
- dev=PNP_DEV(0x4e, W83627EHG_HWM);
+ dev = PNP_DEV(0x4e, W83627EHG_HWM);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 4c74e4e..3f9d7c7 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 7b00176..09e4ec7 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
index d21a7e0..69dd16d 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c
@@ -57,7 +57,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[0] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
- .devfn = (0x01<<3)|0x0, /* 0x01 is CS5536 */
+ .devfn = (0x01 << 3)|0x0, /* 0x01 is CS5536 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
@@ -81,7 +81,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[1] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
- .devfn = (0x0f<<3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
+ .devfn = (0x0f << 3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_NONE,
@@ -105,7 +105,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[2] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
- .devfn = (0x0e<<3)|0x0, /* 0x0e is eth0 */
+ .devfn = (0x0e << 3)|0x0, /* 0x0e is eth0 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
@@ -129,7 +129,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[3] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
- .devfn = (0x10<<3)|0x0, /* 0x10 is eth1 */
+ .devfn = (0x10 << 3)|0x0, /* 0x10 is eth1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
@@ -153,7 +153,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[4] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
- .devfn = (0x11<<3)|0x0, /* 0x11 is SATA */
+ .devfn = (0x11 << 3)|0x0, /* 0x11 is SATA */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
@@ -184,7 +184,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[5] = {
.slot = 0x1, /* This is real PCI slot. */
.bus = 0x00,
- .devfn = (0x09<<3)|0x0, /* 0x09 is PCI1 */
+ .devfn = (0x09 << 3)|0x0, /* 0x09 is PCI1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
@@ -210,7 +210,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[6] = {
.slot = 0x2, /* This is real PCI slot. */
.bus = 0x00,
- .devfn = (0x0a<<3)|0x0, /* 0x0a is PCI2 */
+ .devfn = (0x0a << 3)|0x0, /* 0x0a is PCI2 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
@@ -236,7 +236,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[7] = {
.slot = 0x3, /* This is real PCI slot. */
.bus = 0x00,
- .devfn = (0x0b<<3)|0x0, /* 0x0b is PCI3 */
+ .devfn = (0x0b << 3)|0x0, /* 0x0b is PCI3 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQC,
@@ -262,7 +262,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
[8] = {
.slot = 0x4, /* This is real PCI slot. */
.bus = 0x00,
- .devfn = (0x0c<<3)|0x0, /* 0x0c is PCI4 */
+ .devfn = (0x0c << 3)|0x0, /* 0x0c is PCI4 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index 56ca33a..1afc517 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -144,7 +144,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { {
0x10EC0262, /* Vendor ID/Device IDA */
0x0000, /* SubSystem ID */
0xFF, /* Revision IDA */
- 0x01, /* Front panel support (1=yes, 2=no) */
+ 0x01, /* Front panel support (1 = yes, 2 = no) */
0x000B, /* Number of Rear Jacks = 11 */
0x0002 /* Number of Front Jacks = 2 */
},
diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c
index 7c87f9f..1a7e85b 100644
--- a/src/mainboard/intel/d945gclf/irq_tables.c
+++ b/src/mainboard/intel/d945gclf/irq_tables.c
@@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*18, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b0, /* Device */
@@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
- {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
- {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
- {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
- {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
- {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
- {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
- {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
- {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
- {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
- {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
- {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
- {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
- {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
- {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
- {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+ {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+ {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+ {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+ {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+ {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+ {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+ {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+ {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+ {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+ {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+ {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+ {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+ {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+ {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
}
};
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
index 608489b..79ca0a4 100644
--- a/src/mainboard/intel/eagleheights/debug.c
+++ b/src/mainboard/intel/eagleheights/debug.c
@@ -61,13 +61,13 @@ static inline void siodump(void)
unsigned char data;
printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");
- for (i=0x10; i<=0x2d; i++) {
+ for (i = 0x10; i <= 0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
- for (i=0xf0; i<=0xff; i++) {
+ for (i = 0xf0; i <= 0xff; i++) {
print_reg((unsigned char)i);
}
@@ -82,7 +82,7 @@ static inline void siodump(void)
#endif
printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
- for (i=0xf0; i<=0xf8; i++) {
+ for (i = 0xf0; i <= 0xf8; i++) {
print_reg((unsigned char)i);
}
printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n");
diff --git a/src/mainboard/intel/littleplains/irq_tables.c b/src/mainboard/intel/littleplains/irq_tables.c
index 538478d..bca68ea 100644
--- a/src/mainboard/intel/littleplains/irq_tables.c
+++ b/src/mainboard/intel/littleplains/irq_tables.c
@@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x0F1C, /* Device */
@@ -41,19 +41,19 @@ const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x86, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
- {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
- {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
- {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
- {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
- {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
- {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
- {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
- {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
+ {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
+ {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
+ {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
+ {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
+ {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
+ {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
}
};
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
index d0f1b1f..b17f57c 100644
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ b/src/mainboard/intel/minnowmax/gpio.c
@@ -175,7 +175,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S5[02] - SOC_GPIO_S5_2 */
GPIO_FUNC6, /* GPIO_S5[03] - mPCIE_WAKEB */
GPIO_NC, /* GPIO_S5[04] - No Connect */
- GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/
+ GPIO_INPUT, /* GPIO_S5[05] - BOM_OP1 - Memory: 0 = 1GB 1 = 2GB or 4GB*/
GPIO_INPUT, /* GPIO_S5[06] - BOM_OP2 */
GPIO_INPUT, /* GPIO_S5[07] - BOM_OP3 */
GPIO_OUT_HIGH_LEGACY, /* GPIO_S5[08] - SOC_USB_HOST_EN0 */
diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c
index 538478d..bca68ea 100644
--- a/src/mainboard/intel/mohonpeak/irq_tables.c
+++ b/src/mainboard/intel/mohonpeak/irq_tables.c
@@ -33,7 +33,7 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x0F1C, /* Device */
@@ -41,19 +41,19 @@ const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x86, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
- {0x00,(0x02<<3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
- {0x00,(0x03<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x04<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x0b<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
- {0x00,(0x0f<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
- {0x00,(0x13<<3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
- {0x00,(0x14<<3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
- {0x00,(0x16<<3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
- {0x00,(0x17<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
- {0x00,(0x18<<3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
- {0x00,(0x1f<<3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
+ {0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
+ {0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
+ {0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
+ {0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
+ {0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
+ {0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
+ {0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
+ {0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
}
};
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 5788e34..ee9d1c2 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -47,31 +47,31 @@ static void *smp_write_config_table(void *v)
/* Internal PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
+ 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
+ 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
+ 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
+ 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
+ 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
+ 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
+ 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
+ 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
+ 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
+ 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
+ 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
+ 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
+ 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */
/* PCI slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
diff --git a/src/mainboard/intel/stargo2/gpio.h b/src/mainboard/intel/stargo2/gpio.h
index 25ecfeb..9651655 100644
--- a/src/mainboard/intel/stargo2/gpio.h
+++ b/src/mainboard/intel/stargo2/gpio.h
@@ -165,9 +165,9 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio37 = GPIO_MODE_NONE, /* Unused */
.gpio38 = GPIO_MODE_GPIO, /* Dev Kit Board Version high bit */
.gpio39 = GPIO_MODE_GPIO, /* Dev Kit Board Version low bit */
- .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N<1> */
- .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N<2> */
- .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N<3> */
+ .gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N <1> */
+ .gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N <2> */
+ .gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N <3> */
.gpio43 = GPIO_MODE_NONE, /* Unused */
.gpio44 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO1_SUS : MLR TODO */
.gpio45 = GPIO_MODE_NONE, /* Unused */
@@ -184,7 +184,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio56 = GPIO_MODE_GPIO, /* CONN_GBE_RESET_N */
.gpio57 = GPIO_MODE_NONE, /* Unused */
.gpio58 = GPIO_MODE_NATIVE, /* PCH_SML1_CLK */
- .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N<0> */
+ .gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N <0> */
.gpio60 = GPIO_MODE_NONE, /* Unused */
.gpio61 = GPIO_MODE_NATIVE, /* PCH_SUS_STAT_N */
.gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK */
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index f6cf1cf..ca934b3 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -75,50 +75,50 @@ static void *smp_write_config_table(void *v)
/* IMCH/IICH PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
+ 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
+ 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
+ 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
+ 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
+ 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
+ 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */
if (bus_pea0) {
/* PCIe slot 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea0, (0<<2)|0, 0x8, 0x10);
+ bus_pea0, (0 << 2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea0, (0<<2)|1, 0x8, 0x11);
+ bus_pea0, (0 << 2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea0, (0<<2)|2, 0x8, 0x12);
+ bus_pea0, (0 << 2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea0, (0<<2)|3, 0x8, 0x13);
+ bus_pea0, (0 << 2)|3, 0x8, 0x13);
}
if (bus_pea1) {
/* PCIe slots 1-4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea1, (0<<2)|0, 0x8, 0x10);
+ bus_pea1, (0 << 2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea1, (0<<2)|1, 0x8, 0x11);
+ bus_pea1, (0 << 2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea1, (0<<2)|2, 0x8, 0x12);
+ bus_pea1, (0 << 2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_pea1, (0<<2)|3, 0x8, 0x13);
+ bus_pea1, (0 << 2)|3, 0x8, 0x13);
}
if (bus_aioc) {
/* AIOC PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
+ bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
+ bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
+ bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */
}
/* There is no extension information... */
diff --git a/src/mainboard/intel/wtm2/graphics.c b/src/mainboard/intel/wtm2/graphics.c
index d51184b..46f8ff4 100644
--- a/src/mainboard/intel/wtm2/graphics.c
+++ b/src/mainboard/intel/wtm2/graphics.c
@@ -23,7 +23,7 @@ void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
io_i915_write32(0x80000000,0x45400);
io_i915_write32(0x00000000,_CURACNTR);
- io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
+ io_i915_write32((/* PIPEA */0x0 << 24)|0x00000000,_DSPACNTR);
io_i915_write32(0x00000000,_DSPBCNTR);
io_i915_write32(0x80000000,CPU_VGACNTRL);
io_i915_write32(0x00000000,_DSPASIZE+0xc);
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
index 9750d08..a5c0c9c 100644
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ b/src/mainboard/iwave/iWRainbowG6/romstage.c
@@ -219,7 +219,7 @@ void transaction3(unsigned char dev_addr)
// sch_SMbus_regs ();
//check the status register for busy state
- //temp=inb(SMBusBase+SMBHSTSTS);
+ //temp = inb(SMBusBase+SMBHSTSTS);
//printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
//sch_SMbus_regs ();
//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c
index 7c8835a..5b2b2b0 100644
--- a/src/mainboard/iwill/dk8_htx/acpi_tables.c
+++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c
@@ -24,7 +24,7 @@
unsigned long acpi_fill_madt(unsigned long current)
{
- unsigned int gsi_base=0x18;
+ unsigned int gsi_base = 0x18;
struct mb_sysconf_t *m;
@@ -66,7 +66,7 @@ unsigned long acpi_fill_madt(unsigned long current)
int i;
int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
+ for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
@@ -144,11 +144,11 @@ unsigned long mainboard_write_acpi_tables(device_t device,
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
+ for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
uint8_t c;
- if(i<7) {
+ if(i < 7) {
c = (uint8_t) ('4' + i - 1);
}
else {
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
index 43d7c16..c7d649a 100644
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ b/src/mainboard/iwill/dk8_htx/fadt.c
@@ -23,13 +23,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
+ header->asl_compiler_revision = 0;
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
- // 3=Workstation,4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile=0x03;
- fadt->sci_int=9;
+ // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0;
diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c
index e9f13b4..2f1dade 100644
--- a/src/mainboard/iwill/dk8_htx/irq_tables.c
+++ b/src/mainboard/iwill/dk8_htx/irq_tables.c
@@ -111,7 +111,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num++;
//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
// pirq_info++; slot_num++;
int j = 0;
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index eecad5c..9361a58 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
+ for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) {
@@ -87,47 +87,47 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
// Onboard VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12);
//Slot 5 PCI 32
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+ for(i = 0; i < 4; i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
}
//Slot 6 PCI 32
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+ for(i = 0; i < 4; i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
}
//Slot 1: HTX
//Slot 2 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
+ for(i = 0; i < 4; i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30
}
//Slot 3 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
+ for(i = 0; i < 4; i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
}
//Slot 4 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
+ for(i = 0; i < 4; i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26
}
//Onboard NICS
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24
//Onboard SATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25
j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
+ for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
int ii;
device_t dev;
@@ -140,8 +140,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
//Slot 1 PCI-X 133/100/66
- for(ii=0;ii<4;ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+ for(ii = 0; ii < 4; ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
}
}
}
@@ -151,8 +151,8 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
//Slot 2 PCI-X 133/100/66
- for(ii=0;ii<4;ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+ for(ii = 0; ii < 4; ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
}
}
}
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 4cf89b1..fa0c11c 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -28,12 +28,12 @@ static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -42,7 +42,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
@@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// show final fid and vid
{
msr_t msr;
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
diff --git a/src/mainboard/jetway/j7f2/irq_tables.c b/src/mainboard/jetway/j7f2/irq_tables.c
index c66e971..15263cc 100644
--- a/src/mainboard/jetway/j7f2/irq_tables.c
+++ b/src/mainboard/jetway/j7f2/irq_tables.c
@@ -30,17 +30,17 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x3e, /* Checksum */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
- {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
- {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
- {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
+ {0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
+ {0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+ {0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
+ {0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
+ {0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+ {0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
}
};
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c
index 0de239c..c7e2fe9 100644
--- a/src/mainboard/jetway/j7f2/romstage.c
+++ b/src/mainboard/jetway/j7f2/romstage.c
@@ -53,7 +53,7 @@ static void enable_mainboard_devices(void)
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
- /* bit=0 means enable function (per CX700 datasheet)
+ /* bit = 0 means enable function (per CX700 datasheet)
* 5 16.1 USB 2
* 4 16.0 USB 1
* 3 15.0 SATA and PATA
@@ -62,7 +62,7 @@ static void enable_mainboard_devices(void)
*/
pci_write_config8(dev, 0x50, 0x80);
- /* bit=1 means enable internal function (per CX700 datasheet)
+ /* bit = 1 means enable internal function (per CX700 datasheet)
* 3 Internal RTC
* 2 Internal PS2 Mouse
* 1 Internal KBC Configuration
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 37caa6e..44c41fd 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -66,10 +66,10 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
/* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
- Data16=Data8<<8;
+ Data16 = Data8 << 8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
- Data16|=Data8;
+ Data16 |= Data8;
AcpiMmioAddr = (uint32_t)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 0db35ce..895057b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -134,7 +134,7 @@ chip northbridge/amd/agesa/family14/root_complex
#
# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
# with i2cdump tool.
-# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+# Notes: 0xa0 = 0x50*2, 0xa2 = 0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
#
register "spdAddrLookup" = "
{
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index 0afd86e..59e7e9f 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 8c87563..43e88d1 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3A);
/* show final fid and vid */
- msr=rdmsr(0xc0010071);
+ msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c
index 2e59f93..0c5f403 100644
--- a/src/mainboard/kontron/986lcd-m/irq_tables.c
+++ b/src/mainboard/kontron/986lcd-m/irq_tables.c
@@ -20,7 +20,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b0, /* Device */
@@ -28,25 +28,25 @@ static const struct irq_routing_table intel_irq_routing_table = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
- {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
- {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
- {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
- {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
- {0x00,(0x1b<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
- {0x00,(0x1c<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
- {0x04,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
- {0x04,(0x01<<3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
- {0x04,(0x02<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
- {0x04,(0x03<<3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
- {0x04,(0x04<<3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
- {0x04,(0x05<<3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
- {0x04,(0x06<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
- {0x04,(0x09<<3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
- {0x01,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
- {0x02,(0x00<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
+ {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
+ {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
+ {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
+ {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
+ {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
+ {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
+ {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
+ {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
+ {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
+ {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
+ {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
+ {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
+ {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
+ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
+ {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
}
};
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 3dcf4cc..e9143a8 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -57,7 +57,7 @@ static void ich7_enable_lpc(void)
{
int lpt_en = 0;
if (read_option(lpt, 0) != 0) {
- lpt_en = 1<<2; // enable LPT
+ lpt_en = 1 << 2; // enable LPT
}
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
@@ -98,7 +98,7 @@ static void early_superio_config_w83627thg(void)
{
device_t dev;
- dev=PNP_DEV(0x2e, W83627THG_SP1);
+ dev = PNP_DEV(0x2e, W83627THG_SP1);
pnp_enter_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
@@ -106,14 +106,14 @@ static void early_superio_config_w83627thg(void)
pnp_write_config(dev, 0x29, 0x43); // GPIO settings
pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
- dev=PNP_DEV(0x2e, W83627THG_SP1);
+ dev = PNP_DEV(0x2e, W83627THG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_SP2);
+ dev = PNP_DEV(0x2e, W83627THG_SP2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
@@ -121,7 +121,7 @@ static void early_superio_config_w83627thg(void)
// pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_KBC);
+ dev = PNP_DEV(0x2e, W83627THG_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@@ -129,33 +129,33 @@ static void early_superio_config_w83627thg(void)
// pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
+ dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x2e, W83627THG_GPIO2);
+ dev = PNP_DEV(0x2e, W83627THG_GPIO2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it
- dev=PNP_DEV(0x2e, W83627THG_GPIO3);
+ dev = PNP_DEV(0x2e, W83627THG_GPIO3);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
- dev=PNP_DEV(0x2e, W83627THG_FDC);
+ dev = PNP_DEV(0x2e, W83627THG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x2e, W83627THG_PP);
+ dev = PNP_DEV(0x2e, W83627THG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
/* Enable HWM */
- dev=PNP_DEV(0x2e, W83627THG_HWM);
+ dev = PNP_DEV(0x2e, W83627THG_HWM);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
@@ -163,7 +163,7 @@ static void early_superio_config_w83627thg(void)
pnp_exit_func_mode(dev);
- dev=PNP_DEV(0x4e, W83627THG_SP1);
+ dev = PNP_DEV(0x4e, W83627THG_SP1);
pnp_enter_func_mode(dev);
pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
@@ -172,22 +172,22 @@ static void early_superio_config_w83627thg(void)
pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627THG_SP2);
+ dev = PNP_DEV(0x4e, W83627THG_SP2);
pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
pnp_set_enable(dev, 1);
- dev=PNP_DEV(0x4e, W83627THG_FDC);
+ dev = PNP_DEV(0x4e, W83627THG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627THG_PP);
+ dev = PNP_DEV(0x4e, W83627THG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
- dev=PNP_DEV(0x4e, W83627THG_KBC);
+ dev = PNP_DEV(0x4e, W83627THG_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c
index f9768b2..b397f52 100644
--- a/src/mainboard/kontron/kt690/fadt.c
+++ b/src/mainboard/kontron/kt690/fadt.c
@@ -56,7 +56,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
- /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
/* disable system management mode by setting to 0: */
@@ -85,11 +85,11 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
- pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+ pm_iowrite(0x0E, 1 << 3 | 0 << 2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at
* index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/
- pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ pm_iowrite(0x10, 1 << 1 | 1 << 3| 1 << 5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 39192b0..8895163 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v)
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
- /* dword |= 1<<22; PIC and APIC co exists */
+ /* dword |= 1 << 22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index cb33e3b..d25799f 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
enable_fid_change();
@@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
init_fidvid_bsp(bsp_apicid);
/* show final fid and vid */
- msr=rdmsr(0xc0010042);
+ msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
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