[coreboot-gerrit] New patch to review for coreboot: intel/amenia: Remove Amenia mainboard
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Fri Sep 23 03:18:29 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16725
-gerrit
commit a1f03cf1bde519ad98d6ad8c9b088331df32e0f7
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Thu Sep 22 18:13:24 2016 -0700
intel/amenia: Remove Amenia mainboard
The mainboard is not being worked on anymore, not available outside of
Intel and thus has litle practical use. Remove mainboard code completely.
Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
MAINTAINERS | 5 -
src/mainboard/intel/amenia/Kconfig | 65 ------
src/mainboard/intel/amenia/Kconfig.name | 2 -
src/mainboard/intel/amenia/Makefile.inc | 12 -
src/mainboard/intel/amenia/acpi/dptf.asl | 94 --------
src/mainboard/intel/amenia/acpi/ec.asl | 26 ---
src/mainboard/intel/amenia/acpi/mainboard.asl | 121 ----------
src/mainboard/intel/amenia/acpi/superio.asl | 25 --
src/mainboard/intel/amenia/acpi_tables.c | 14 --
src/mainboard/intel/amenia/board_info.txt | 4 -
src/mainboard/intel/amenia/bootblock.c | 31 ---
src/mainboard/intel/amenia/chromeos.c | 61 -----
src/mainboard/intel/amenia/chromeos.fmd | 52 -----
src/mainboard/intel/amenia/chromeos_ramstage.c | 31 ---
src/mainboard/intel/amenia/devicetree.cb | 125 ----------
src/mainboard/intel/amenia/dsdt.asl | 56 -----
src/mainboard/intel/amenia/ec.c | 52 -----
src/mainboard/intel/amenia/ec.h | 71 ------
src/mainboard/intel/amenia/gpio.h | 304 -------------------------
src/mainboard/intel/amenia/mainboard.c | 76 -------
src/mainboard/intel/amenia/on_board.h | 27 ---
src/mainboard/intel/amenia/romstage.c | 114 ----------
src/mainboard/intel/amenia/smihandler.c | 36 ---
23 files changed, 1404 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6e51ff8..750fcff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -246,11 +246,6 @@ M: Hannah Williams <hannah.williams at intel.com>
S: Supported
F: /src/mainboard/intel/strago/
-INTEL AMENIA MAINBOARD
-M: Andrey Petrov <andrey.petrov at intel.com>
-S: Supported
-F: src/mainboard/intel/amenia/
-
INTEL BRASWELL SOC
M: Hannah Williams <hannah.williams at intel.com>
S: Supported
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
deleted file mode 100644
index 5d50d7b..0000000
--- a/src/mainboard/intel/amenia/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-if BOARD_INTEL_AMENIA
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select SOC_INTEL_APOLLOLAKE
- select BOARD_ROMSIZE_KB_16384
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_LPC
- select EC_GOOGLE_CHROMEEC_PD
- select HAVE_ACPI_TABLES
- select MAINBOARD_HAS_LPC_TPM
- select HAVE_ACPI_RESUME
- select MAINBOARD_HAS_CHROMEOS
- select SYSTEM_TYPE_LAPTOP
- select TPM_ON_FAST_SPI
-
-config CHROMEOS
- select LID_SWITCH
-
-config MAINBOARD_DIR
- string
- default intel/amenia
-
-config MAINBOARD_FAMILY
- string
- default "Intel_Amenia"
-
-config MAINBOARD_PART_NUMBER
- string
- default "Amenia"
-
-config MAINBOARD_VENDOR
- string
- default "Intel"
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "AMENIA TEST"
-
-config FMAP_FILE
- string
- default "amenia"
-
-config MAX_CPUS
- int
- default 8
-
-config INCLUDE_NHLT_BLOBS
- bool "Include blobs for audio."
- select NHLT_DMIC_2CH_16B
- select NHLT_DA7219
- select NHLT_MAX98357
-
-config DRIVERS_GENERIC_MAX98357A
- default y
-
-config DRIVERS_I2C_DA7219
- default y
-
-config UART_FOR_CONSOLE
- int
- default 2
-
-endif # BOARD_INTEL_AMENIA
diff --git a/src/mainboard/intel/amenia/Kconfig.name b/src/mainboard/intel/amenia/Kconfig.name
deleted file mode 100644
index 183b17c..0000000
--- a/src/mainboard/intel/amenia/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_AMENIA
- bool "Amenia"
diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc
deleted file mode 100644
index a67b986..0000000
--- a/src/mainboard/intel/amenia/Makefile.inc
+++ /dev/null
@@ -1,12 +0,0 @@
-bootblock-y += bootblock.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-ramstage-y += mainboard.c
-ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/intel/amenia/acpi/dptf.asl b/src/mainboard/intel/amenia/acpi/dptf.asl
deleted file mode 100644
index a75d668..0000000
--- a/src/mainboard/intel/amenia/acpi/dptf.asl
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define DPTF_CPU_PASSIVE 80
-#define DPTF_CPU_CRITICAL 90
-#define DPTF_CPU_ACTIVE_AC0 90
-#define DPTF_CPU_ACTIVE_AC1 80
-#define DPTF_CPU_ACTIVE_AC2 70
-#define DPTF_CPU_ACTIVE_AC3 60
-#define DPTF_CPU_ACTIVE_AC4 50
-
-#define DPTF_TSR0_SENSOR_ID 0
-#define DPTF_TSR0_SENSOR_NAME "Battery"
-#define DPTF_TSR0_PASSIVE 48
-#define DPTF_TSR0_CRITICAL 70
-
-#define DPTF_TSR1_SENSOR_ID 1
-#define DPTF_TSR1_SENSOR_NAME "Ambient"
-#define DPTF_TSR1_PASSIVE 60
-#define DPTF_TSR1_CRITICAL 70
-
-#define DPTF_TSR2_SENSOR_ID 2
-#define DPTF_TSR2_SENSOR_NAME "Charger"
-#define DPTF_TSR2_PASSIVE 55
-#define DPTF_TSR2_CRITICAL 70
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
- Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
- Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
- Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
- Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
-})
-
-Name (DTRT, Package () {
- /* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
- /* Charger Effect on Temp Sensor 1 */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
- /* CPU Effect on Temp Sensor 1 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
- 0x2, /* Revision */
- Package () { /* Power Limit 1 */
- 0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 1600, /* PowerLimitMinimum */
- 12000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 200 /* StepSize */
- },
- Package () { /* Power Limit 2 */
- 1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 6000, /* PowerLimitMinimum */
- 8000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 1000 /* StepSize */
- }
-})
-
-/* Include soc specific DPTF changes */
-#include <soc/intel/apollolake/acpi/dptf.asl>
-/* Include common dptf ASL files */
-#include <soc/intel/common/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl
deleted file mode 100644
index fe53cb5..0000000
--- a/src/mainboard/intel/amenia/acpi/ec.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include "../ec.h"
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
deleted file mode 100644
index 80f8f26..0000000
--- a/src/mainboard/intel/amenia/acpi/mainboard.asl
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <on_board.h>
-#include "../ec.h"
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name (_HID, EisaId ("PNP0C0D"))
- Method (_LID, 0)
- {
- Return (\_SB.PCI0.LPCB.EC0.LIDS)
- }
- Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
- }
-
- Device (PWRB)
- {
- Name (_HID, EisaId ("PNP0C0C"))
- }
-}
-
-Scope (\_SB.PCI0.I2C4)
-{
- /* Standard Mode: HCNT, LCNT, SDA Hold Register */
- /* SDA Hold register value of 40 indicates
- * sda hold time of 0.3us for ic_clk of 133MHz
- */
- Name (SSCN, Package () { 0, 0, 40 })
-
- /* Fast Mode: HCNT, LCNT, SDA Hold Register */
- /* SDA Hold register value of 40 indicates
- * sda hold time of 0.3us for ic_clk of 133MHz
- */
- Name (FMCN, Package () { 0, 0, 40 })
-
- Device (ETPA)
- {
- Name (_HID, "ELAN0000")
- Name (_DDN, "Elan Touchpad")
- Name (_UID, 1)
- Name (ISTP, 1) /* Touchpad */
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x15, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C4", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- TOUCHPAD_INT
- }
- })
-
- Method (_STA)
- {
- Return (0xF)
- }
-
- }
-}
-
-Scope (\_SB.PCI0.I2C3)
-{
- Device (ETSA)
- {
- Name (_HID, "ELAN0001")
- Name (_DDN, "Elan Touchscreen")
- Name (_UID, 1)
- Name (ISTP, 0) /* TouchScreen */
- Name (_S0W, 4)
-
- Name (_CRS, ResourceTemplate()
- {
- I2cSerialBus (
- 0x10, // SlaveAddress
- ControllerInitiated, // SlaveMode
- 400000, // ConnectionSpeed
- AddressingMode7Bit, // AddressingMode
- "\\_SB.PCI0.I2C3", // ResourceSource
- )
- Interrupt (ResourceConsumer, Edge, ActiveLow)
- {
- GPIO_21_IRQ
- }
- })
-
- Method (_STA)
- {
- Return (0xF)
- }
- }
-}
-
-/*
- * LPC Trusted Platform Module
- */
-Scope (\_SB.PCI0.LPCB)
-{
- #include <drivers/pc80/tpm/acpi/tpm.asl>
- #include "ec.asl"
-}
diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl
deleted file mode 100644
index db14d17..0000000
--- a/src/mainboard/intel/amenia/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include "../ec.h"
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/intel/amenia/acpi_tables.c b/src/mainboard/intel/amenia/acpi_tables.c
deleted file mode 100644
index 8d4d1cf..0000000
--- a/src/mainboard/intel/amenia/acpi_tables.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Blank file required by build system assumptions of this file being present.
- */
diff --git a/src/mainboard/intel/amenia/board_info.txt b/src/mainboard/intel/amenia/board_info.txt
deleted file mode 100644
index b97ca15..0000000
--- a/src/mainboard/intel/amenia/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Vendor name: Intel
-Board name: Amenia Board
-Category: eval
-Flashrom support: y
diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c
deleted file mode 100644
index c483d77..0000000
--- a/src/mainboard/intel/amenia/bootblock.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <soc/lpc.h>
-
-void bootblock_mainboard_init(void)
-{
- /* Configure pads so that our signals make it out of the SOC. */
- lpc_configure_pads();
-
- /* Ports 62/66, 60/64, and 200->208 are needed by ChromeEC */
- lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
-
- /* Ports 800 -> 9ff are used by ChromeEC. */
- lpc_open_pmio_window(0x800, 0x200);
-}
diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c
deleted file mode 100644
index 4cfc2a6..0000000
--- a/src/mainboard/intel/amenia/chromeos.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "ec.h"
-
-#include <ec/google/chromeec/ec.h>
-#include <soc/gpio_defs.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-int get_lid_switch(void)
-{
- /* Default to force open */
- return 1;
-}
-
-/* The dev-switch is virtual */
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* Recovery mode via ESC + Refresh + PWR ? */
- ec_events = google_chromeec_get_events_b();
- if (ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY))
- return 1;
-
- return 0;
-}
-
-int get_write_protect_state(void)
-{
- return 0;
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
- CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}
diff --git a/src/mainboard/intel/amenia/chromeos.fmd b/src/mainboard/intel/amenia/chromeos.fmd
deleted file mode 100644
index bebee33..0000000
--- a/src/mainboard/intel/amenia/chromeos.fmd
+++ /dev/null
@@ -1,52 +0,0 @@
-FLASH 16M {
- WP_RO at 0x0 0x800000 {
- SI_DESC at 0x0 0x1000
- IFWI at 0x1000 0x1ff000
- RO_SECTION at 0x200000 0x600000 {
- RO_VPD at 0x0 0x4000
- FMAP at 0x4000 0x800
- RO_FRID at 0x4800 0x40
- RO_FRID_PAD at 0x4840 0x7c0
- COREBOOT(CBFS)@0x5000 0x17b000
- GBB at 0x180000 0x40000
- RO_UNUSED_1 at 0x1c0000 0x400000
- # logical boot partition 2. Remove with updated CSE
- SIGN_CSE at 0x5c0000 0x10000
- RO_UNUSED_2 at 0x5d0000 0x30000
- }
- }
- MISC_RW at 0x800000 0x1a000 {
- RW_MRC_CACHE at 0x0 0x10000
- RW_ELOG at 0x10000 0x4000
- RW_SHARED at 0x14000 0x4000 {
- SHARED_DATA at 0x0 0x2000
- VBLOCK_DEV at 0x2000 0x2000
- }
- RW_VPD at 0x18000 0x2000
- }
- RW_SECTION_A at 0x81a000 0x28f800 {
- VBLOCK_A at 0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x27f7c0
- RW_FWID_A at 0x28f7c0 0x40
- }
- RW_SECTION_B at 0xaa9800 0x28f800 {
- VBLOCK_B at 0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x27f7c0
- RW_FWID_B at 0x28f7c0 0x40
- }
- RW_NVRAM at 0xd39000 0x6000
- RW_LEGACY(CBFS)@0xd3f000 0x200000
- BIOS_UNUSABLE at 0xf3f000 0x40000
- DEVICE_EXTENSION at 0xf7f000 0x80000
- # Currently, it is required that the BIOS region be a multiple of 8KiB.
- # This is required so that the recovery mechanism can find SIGN_CSE
- # region aligned to 4K at the center of BIOS region. Since the
- # descriptor at the beginning uses 4K and BIOS starts at an offset of
- # 4K, a hole of 4K is created towards the end of the flash to compensate
- # for the size requirement of BIOS region.
- # FIT tool thus creates descriptor with following regions:
- # Descriptor --> 0 to 4K
- # BIOS --> 4K to 0xf7f000
- # Device ext --> 0xf7f000 to 0xfff000
- UNUSED_HOLE at 0xfff000 0x1000
-}
diff --git a/src/mainboard/intel/amenia/chromeos_ramstage.c b/src/mainboard/intel/amenia/chromeos_ramstage.c
deleted file mode 100644
index dcc6b90..0000000
--- a/src/mainboard/intel/amenia/chromeos_ramstage.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {-1, ACTIVE_HIGH, 0, "write protect"},
- {-1, ACTIVE_HIGH, 0, "recovery"},
- {-1, ACTIVE_HIGH, 1, "developer"},
- {-1, ACTIVE_HIGH, 1, "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, 0, "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
deleted file mode 100644
index 351aa5a..0000000
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ /dev/null
@@ -1,125 +0,0 @@
-chip soc/intel/apollolake
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
- register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
- register "pcie_rp2_clkreq_pin" = "0" # SSD
-
- # GPIO for PERST_0
- # If PERST_0 is defined assign the GPIO
- # If PERST_0 is not defined assign GPIO_PRT0_UDEF
- register "prt0_gpio" = "GPIO_122"
-
- # eMMC TX DATA Delay 1#
- # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
- # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
- register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
-
- # eMMC TX DATA Delay 2#
- # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
- # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
- # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
- # 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode
- register "emmc_tx_data_cntl2" = "0x1c1c1c00"
-
- # eMMC RX CMD/DATA Delay 1#
- # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
- # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
- # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
- # 0x00[6:0] stands for 0 delay for SDR12/Compatibility
- register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00"
-
- # eMMC RX CMD/DATA Delay 2#
- # 0x01[17:16] stands for Rx Clock before Output Buffer
- # 0x00[14:8] stands for 0 delay for Auto Tuning Mode
- # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200
- register "emmc_rx_cmd_data_cntl2" = "0x1001c"
-
- # LPSS S0ix Enable
- register "lpss_s0ix_enable" = "1"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route, i.e., if this route changes then the affected GPE
- # offset bits also need to be changed. This sets the PMC register
- # GPE_CFG fields.
- register "gpe0_dw1" = "PMC_GPE_N_31_0"
- register "gpe0_dw2" = "PMC_GPE_N_63_32"
- register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
- # Enable DPTF
- register "dptf_enable" = "1"
-
- device domain 0 on
- device pci 00.0 on end # - Host Bridge
- device pci 00.1 on end # - DPTF
- device pci 00.2 on end # - NPK
- device pci 02.0 on end # - Gen
- device pci 03.0 on end # - Iunit
- device pci 0d.0 on end # - P2SB
- device pci 0d.1 on end # - PMC
- device pci 0d.2 on end # - SPI
- device pci 0d.3 on end # - Shared SRAM
- device pci 0e.0 on # - Audio
- chip drivers/generic/max98357a
- register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)"
- device generic 0 on end
- end
- end
- device pci 11.0 off end # - ISH
- device pci 12.0 on end # - SATA
- device pci 13.0 off end # - PCIe-A 0
- device pci 13.1 off end # - PCIe-A 1
- device pci 13.2 off end # - PCIe-A 2 - Onboard Lan
- device pci 13.3 off end # - PCIe-A 3
- device pci 14.0 on end # - PCIe-B 0 - wifi
- device pci 14.1 off end # - PCIe-B 1 - Onboard M2 Slot(Wifi/BT)
- device pci 15.0 on end # - XHCI
- device pci 15.1 off end # - XDCI
- device pci 16.0 on # - I2C 0
- chip drivers/i2c/da7219
- register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
- register "btn_cfg" = "50"
- register "mic_det_thr" = "500"
- register "jack_ins_deb" = "20"
- register "jack_det_rate" = ""32ms_64ms""
- register "jack_rem_deb" = "1"
- register "a_d_btn_thr" = "0xa"
- register "d_b_btn_thr" = "0x16"
- register "b_c_btn_thr" = "0x21"
- register "c_mic_btn_thr" = "0x3e"
- register "btn_avg" = "4"
- register "adc_1bit_rpt" = "1"
- register "micbias_lvl" = "2600"
- register "mic_amp_in_sel" = ""diff""
- device i2c 1a on end
- end
- end
- device pci 16.1 on end # - I2C 1
- device pci 16.2 on end # - I2C 2
- device pci 16.3 on end # - I2C 3
- device pci 17.0 on end # - I2C 4
- device pci 17.1 on end # - I2C 5
- device pci 17.2 on end # - I2C 6
- device pci 17.3 on end # - I2C 7
- device pci 18.0 on end # - UART 0
- device pci 18.1 on end # - UART 1
- device pci 18.2 on end # - UART 2
- device pci 18.3 on end # - UART 3
- device pci 19.0 on end # - SPI 0
- device pci 19.1 on end # - SPI 1
- device pci 19.2 on end # - SPI 2
- device pci 1a.0 on end # - PWM
- device pci 1b.0 on end # - SDCARD
- device pci 1c.0 on end # - eMMC
- device pci 1e.0 off end # - SDIO
- device pci 1f.0 on # - LPC
- chip ec/google/chromeec
- device pnp 0c09.0 on end
- end
- end
- device pci 1f.1 on end # - SMBUS
- end
-end
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
deleted file mode 100644
index ab922ab..0000000
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x02, // DSDT revision: ACPI v2.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20110725 // OEM revision
-)
-{
- /* global NVS and variables */
- #include <soc/intel/apollolake/acpi/globalnvs.asl>
-
- /* CPU */
- #include <soc/intel/apollolake/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <soc/intel/apollolake/acpi/northbridge.asl>
- #include <soc/intel/apollolake/acpi/southbridge.asl>
- #include <soc/intel/apollolake/acpi/pch_hda.asl>
- }
- }
-
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
- /* Mainboard Specific devices */
- #include "acpi/mainboard.asl"
-
- /* Chipset specific sleep states */
- #include <soc/intel/apollolake/acpi/sleepstates.asl>
-
- #include "acpi/superio.asl"
-
- Scope (\_SB) {
- /* Dynamic Platform Thermal Framework */
- #include "acpi/dptf.asl"
- }
-}
diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c
deleted file mode 100644
index 7055936..0000000
--- a/src/mainboard/intel/amenia/ec.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- * Copyright (C) 2015 Google Inc.
- * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include "ec.h"
-
-void mainboard_ec_init(void)
-{
- printk(BIOS_ERR, "mainboard: EC init\n");
- post_code(0xf0);
-
- if (acpi_is_wakeup_s3()) {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S3_WAKE_EVENTS);
-
- /* Disable SMI and wake events */
- google_chromeec_set_smi_mask(0);
-
- /* Clear pending events */
- while (google_chromeec_get_event() != 0)
- ;
-
- /* Restore SCI event mask */
- google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
- } else {
- google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
- MAINBOARD_EC_S5_WAKE_EVENTS);
- }
-
- /* Clear wake event mask */
- google_chromeec_set_wake_mask(0);
- post_code(0xf1);
-}
diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h
deleted file mode 100644
index d23ed07..0000000
--- a/src/mainboard/intel/amenia/ec.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
-
-#include <ec/google/chromeec/ec_commands.h>
-
-/*
- * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
- * which is North community
- */
-#define EC_SCI_GPI GPE0_DW1_11
-
-/* GPIO_22 is the EC_SOC_WAKE and is used to wake up from S3 on LID open */
-#define GPE_EC_WAKE GPE0_DW1_22
-
-#define MAINBOARD_EC_SCI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU))
-
-#define MAINBOARD_EC_SMI_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
-
-/* EC can wake from S5 with lid or power button */
-#define MAINBOARD_EC_S5_WAKE_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
-
-/* EC can wake from S3 with lid or power button or key press */
-#define MAINBOARD_EC_S3_WAKE_EVENTS \
- (MAINBOARD_EC_S5_WAKE_EVENTS |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
-
-/* Log EC wake events plus EC shutdown events */
-#define MAINBOARD_EC_LOG_EVENTS \
- (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
-
-#ifndef __ACPI__
-extern void mainboard_ec_init(void);
-#endif
-
-#endif
diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h
deleted file mode 100644
index 3eb4103..0000000
--- a/src/mainboard/intel/amenia/gpio.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-#include <soc/gpio.h>
-
-static const struct pad_config gpio_table[] = {
- /** South West Community **/
- /* PCIe WAKE */
- PAD_CFG_NF(GPIO_205, NATIVE, DEEP, NF1), /* PCIE_WLAN_WAKE3_N */
- PAD_NC(GPIO_206, UP_20K), /* PCIE_WAKE1_B */
- PAD_NC(GPIO_207, UP_20K), /* PCIE_WAKE2_B */
- PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_SSD_WAKE0_N */
- /* eMMC */
- PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */
- PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */
- PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC0_D1 */
- PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC0_D2 */
- PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC0_D3 */
- PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC0_D4 */
- PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC0_D5 */
- PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC0_D6 */
- PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC0_D7 */
- PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */
- PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
- /* SDIO */
- PAD_NC(GPIO_166, DN_20K), /* SDIO_CLK */
- PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */
- /* Configure SDIO to enable power gating */
- PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
- PAD_NC(GPIO_169, DN_20K), /* SDIO_D2 */
- PAD_NC(GPIO_170, DN_20K), /* SDIO_D3 */
- PAD_NC(GPIO_171, DN_20K), /* SDIO_CMD */
- /* SD CARD */
- PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */
- PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
- PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
- PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
- PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
- PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_B */
- PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
- PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
- PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */
- PAD_NC(GPIO_186, DN_20K), /* SDCARD_LVL_WP */
- /* SmBus */
- PAD_NC(SMB_ALERTB, UP_20K), /* SMB_ALERTB */
- PAD_NC(SMB_CLK, UP_20K), /* SMB_CLK */
- PAD_NC(SMB_DATA, UP_20K), /* SMB_DATA */
- /* LPC */
- PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */
- PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
- PAD_NC(LPC_CLKOUT1, NONE), /* LPC_CLKOUT1 */
- PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */
- PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), /* LPC_AD1 */
- PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), /* LPC_AD2 */
- PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), /* LPC_AD3 */
- PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */
- PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAMEB */
- /** end of South West Community **/
-
- /** West Community **/
- /* I2C lines */
- PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* I2C0_SDA for Audio Codec */
- PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* I2C0_SCL for Audio Codec */
- PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA for NFC*/
- PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL for NFC*/
- PAD_NC(GPIO_128, UP_20K), /* LPSS_I2C2_SDA */
- PAD_NC(GPIO_129, UP_20K), /* LPSS_I2C2_SCL */
- PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* I2C3_SDA for Touch Screen */
- PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* I2C3_SCL for Touchscreen */
- PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* I2C4_SDA for Trackpad */
- PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* I2C4_SCL for Trackpad */
- PAD_NC(GPIO_134, UP_20K), /* LPSS_I2C5_SDA */
- PAD_NC(GPIO_135, UP_20K), /* LPSS_I2C5_SCL */
- PAD_NC(GPIO_136, UP_20K), /* LPSS_I2C6_SDA */
- PAD_NC(GPIO_137, UP_20K), /* LPSS_I2C6_SCL */
- PAD_NC(GPIO_138, UP_20K), /* LPSS_I2C7_SDA */
- PAD_NC(GPIO_139, UP_20K), /* LPSS_I2C7_SCL */
- /* I2S lines */
- PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* I2S6_BCLK_Codec */
- PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* I2S6_SYNC_Codec */
- PAD_CFG_NF(GPIO_148, NATIVE, DEEP, NF2), /* I2S6_SDI_Codec */
- PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* I2S6_SDO_Codec */
- /* Misc */
- PAD_CFG_GPO(GPIO_150, 1, DEEP), /* NFC_RESET_N */
- PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* RSVD (ISH_BASE_ACCEL_INT_N) */
- PAD_CFG_GPI(GPIO_152, UP_20K, DEEP), /* RSVD (ALS_IRQ_N) */
- PAD_NC(GPIO_153, DN_20K), /* ISH_GPIO_7 */
- PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */
- PAD_CFG_GPO(GPIO_155, 1, DEEP), /* RSVD (WIFI_PERST_1P8_N) */
- /* PCIE_CLKREQ */
- PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), /* SSD CLKREQ */
- PAD_NC(GPIO_210, UP_20K), /* PCIE_CLKREQ1_B */
- PAD_NC(GPIO_211, UP_20K), /* PCIE_CLKREQ2_B */
- PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), /* Wifi CLKREQ */
- /* OSC signals */
- PAD_NC(OSC_CLK_OUT_0, DN_20K),
- PAD_NC(OSC_CLK_OUT_1, DN_20K),
- PAD_NC(OSC_CLK_OUT_2, DN_20K),
- PAD_NC(OSC_CLK_OUT_3, DN_20K),
- PAD_NC(OSC_CLK_OUT_4, DN_20K),
- /* PMU */
- PAD_NC(PMU_AC_PRESENT, DN_20K), /* PMU_AC_PRESENT */
- PAD_NC(PMU_BATLOW_B, UP_20K), /* PMU_BATLOW_B */
- PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
- PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
- PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
- PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */
- PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
- PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
- PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
- PAD_NC(PMU_WAKE_B, UP_20K), /* PMU_WAKE_B */
- PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */
- PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */
- /** end of West Community **/
-
- /** North West Community */
- /* DDI */
- PAD_NC(GPIO_187, UP_20K), /* HV_DDI0_DDC_SDA */
- PAD_NC(GPIO_188, UP_20K), /* HV_DDI0_DDC_SCL */
- PAD_NC(GPIO_189, UP_20K), /* HV_DDI1_DDC_SDA */
- PAD_NC(GPIO_190, UP_20K), /* HV_DDI1_DDC_SCL */
- /* DBI */
- PAD_NC(GPIO_191, UP_20K), /* DBI_SDA */
- PAD_NC(GPIO_192, UP_20K), /* DBI_SCL */
- /* Panel 0 */
- PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */
- PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */
- PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */
- /* Panel 1 */
- PAD_NC(GPIO_196, DN_20K), /* PANEL1_VDDEN */
- PAD_NC(GPIO_197, DN_20K), /* PANEL1_BKLTEN */
- PAD_NC(GPIO_198, DN_20K), /* PANEL1_BKLTCTL */
- /* Hot Plug Detect */
- PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* DDI0_HPD */
- PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* DDI1_HPD */
- /* GP_INTD_DSI */
- PAD_NC(GPIO_201, DN_20K), /* GP_INTD_DSI_TE1 */
- PAD_NC(GPIO_202, DN_20K), /* GP_INTD_DSI_TE2 */
- /* USB OC */
- PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */
- PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */
- /* SPI */
- PAD_NC(PMC_SPI_FS0, UP_20K), /* PMC_SPI_FS0 */
- PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */
- PAD_NC(PMC_SPI_FS2, UP_20K), /* PMC_SPI_FS2 */
- PAD_NC(PMC_SPI_RXD, DN_20K), /* PMC_SPI_RXD */
- PAD_NC(PMC_SPI_TXD, DN_20K), /* PMC_SPI_TXD */
- PAD_NC(PMC_SPI_CLK, DN_20K), /* PMC_SPI_CLK */
- /* PMIC */
- PAD_NC(PMIC_PWRGOOD, NONE), /* PMIC_PWRGOOD */
- PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */
- PAD_NC(GPIO_213, NONE), /* PMIC_SDWN_B */
- PAD_NC(GPIO_214, DN_20K), /* PMIC_BCUDISW2 */
- PAD_NC(GPIO_215, DN_20K), /* PMIC_BCUDISCRIT */
- PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* PMIC_THERMTRIP_B */
- PAD_NC(PMIC_STDBY, DN_20K), /* PMIC_STDBY */
- PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */
- PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */
- PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */
- /* I2S1 */
- PAD_NC(GPIO_74, DN_20K), /* I2S1_MCLK */
- PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* SPI_WP_STAT */
- PAD_CFG_GPO(GPIO_76, 0, DEEP), /* I2S1_WS_SYNC -- SPK_PA_EN */
- PAD_NC(GPIO_77, DN_20K), /* I2S1_SDI */
- PAD_NC(GPIO_78, DN_20K), /* I2S1_SDO */
- /* I2S4 or DMIC */
- PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* DMIC_CLK_A1 */
- PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* DMIC_CLK_B1 */
- PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* DMIC_DATA_1 */
- PAD_CFG_NF(GPIO_82, NATIVE, DEEP, NF1), /* DMIC_CLK_AB2 */
- PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* DMIC_DATA_2 */
- PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* MCLK */
- /* I2S2 or Headset amp */
- PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* I2S2_BCLK_AMP */
- PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* I2S2_SYNC_AMP */
- PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* I2S2_SDI_AMP */
- PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* I2S2_SDO_AMP */
- /* I2S3 */
- PAD_NC(GPIO_89, DN_20K), /* I2S3_BCLK */
- PAD_NC(GPIO_90, DN_20K), /* I2S3_WS_SYNC */
- PAD_NC(GPIO_91, DN_20K), /* I2S3_SDI */
- PAD_NC(GPIO_92, DN_20K), /* I2S3_SDO */
- /* Fast SPI */
- PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), /* FST_SPI_CS0_B */
- PAD_NC(GPIO_98, UP_20K), /* FST_SPI_CS1_B */
- PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */
- PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */
- PAD_NC(GPIO_101, UP_20K), /* FST_IO2 */
- PAD_NC(GPIO_102, UP_20K), /* FST_IO3 */
- PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */
- PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), /* FST_SPI_CLK_FB */
- /* GP_SSP_0 / SPI - FP */
- PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1), /* SPI for FP */
- PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1), /* SPI for FP */
- PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_B for TPM */
- PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1), /* SPI for FP */
- PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1), /* SPI for FP */
- /* GP_SSP_1 */
- PAD_NC(GPIO_111, DN_20K), /* GP_SSP_1_CLK */
- PAD_CFG_GPO(GPIO_112, 1, DEEP), /* FP Reset */
- PAD_NC(GPIO_113, DN_20K), /* GP_SSP_1_FS1 */
- PAD_CFG_GPI_APIC_LOW(GPIO_116, UP_20K, DEEP),
- /* AUDIO_CODEC_IRQ_N */
- PAD_NC(GPIO_117, DN_20K), /* GP_SSP_1_TXD */
- /* GP_SSP_2 */
- PAD_NC(GPIO_118, DN_20K), /* GP_SSP_2_CLK */
- PAD_NC(GPIO_119, DN_20K), /* GP_SSP_2_FS0 */
- PAD_NC(GPIO_120, DN_20K), /* GP_SSP_2_FS1 */
- PAD_NC(GPIO_121, DN_20K), /* GP_SSP_2_FS2 */
- PAD_CFG_GPO(GPIO_122, 0, DEEP), /* WIFI PERST_0 */
- PAD_NC(GPIO_123, DN_20K), /* GP_SSP_2_TXD */
- /** end of North West Community */
- /** North Community */
- /* MIPI60 debug */
- PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
- PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
- PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */
- PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */
- PAD_CFG_GPI_SCI_LOW(GPIO_11, UP_20K, DEEP, EDGE_SINGLE),
- /* SOC_WAKE_SCI_N */
- PAD_NC(GPIO_12, DN_20K),
- PAD_NC(GPIO_13, DN_20K),
- PAD_CFG_GPI_APIC_LOW(GPIO_14, UP_20K, DEEP), /* FP INT */
- PAD_NC(GPIO_15, DN_20K),
- PAD_NC(GPIO_16, UP_20K),
- PAD_NC(GPIO_17, UP_20K),
- PAD_CFG_GPI_APIC_LOW(GPIO_18, UP_20K, DEEP),
- /* Trackpad_INT_N */
- PAD_CFG_GPI_APIC_LOW(GPIO_19, UP_20K, DEEP),
- /* Audio_Jack_Present_N */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP),
- /* NFC INT */
- PAD_CFG_GPI_APIC_LOW(GPIO_21, UP_20K, DEEP),
- /* TCH_INT_N */
- PAD_CFG_GPI_SCI_LOW(GPIO_22, UP_20K, DEEP, EDGE_SINGLE),
- /* EC_SOC_WAKE_1P8_N */
- PAD_CFG_GPO(GPIO_23, 1, DEEP), /* GPS_NSTANDBY */
- PAD_CFG_GPO(GPIO_24, 1, DEEP), /* SSD_SATA_DEVSLP */
- PAD_NC(GPIO_25, DN_20K),
- PAD_NC(GPIO_26, DN_20K),
- PAD_CFG_GPO(GPIO_27, 0, DEEP), /* NFC DL REQ */
- PAD_NC(GPIO_28, DN_20K),
- PAD_NC(GPIO_29, DN_20K),
- PAD_CFG_GPI_APIC_LOW(GPIO_30, UP_20K, DEEP),
- /* EC_KBD_IRQ_SOC_N */
- PAD_NC(GPIO_31, DN_20K),
- PAD_CFG_NF(GPIO_32, NATIVE, DEEP, NF5), /* GPS_SUSCLK_32K */
- PAD_CFG_GPI(GPIO_33, UP_20K, DEEP), /* EC_KBD_IRQ_SOC_N */
- PAD_NC(GPIO_34, DN_20K),
- PAD_NC(GPIO_35, DN_20K),
- PAD_CFG_GPO(GPIO_36, 0, DEEP), /* TOUCH_PNL_RST */
- PAD_CFG_NF(GPIO_37, NATIVE, DEEP, NF1), /* SOC_BUZZER */
- PAD_NC(GPIO_38, UP_20K),
- PAD_NC(GPIO_39, UP_20K),
- PAD_NC(GPIO_40, UP_20K),
- PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS_B */
- PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* GPS_UART_RXD */
- PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* GPS_UART_TXD */
- PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* GPS_UART_RTS_B */
- PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* GPS_UART_CTS_N */
- PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
- PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/
- PAD_NC(GPIO_48, UP_20K),
- PAD_CFG_GPI_SMI_LOW(GPIO_49, UP_20K, DEEP, EDGE_SINGLE), /* EC_SMI_N */
- /* Camera interface*/
- PAD_NC(GPIO_62, DN_20K), /* GP_CAMERASB00 */
- PAD_NC(GPIO_63, DN_20K), /* GP_CAMERASB01 */
- PAD_NC(GPIO_64, DN_20K), /* GP_CAMERASB02 */
- PAD_NC(GPIO_65, DN_20K), /* GP_CAMERASB03 */
- PAD_NC(GPIO_66, DN_20K), /* GP_CAMERASB04 */
- PAD_NC(GPIO_67, DN_20K), /* GP_CAMERASB05 */
- PAD_NC(GPIO_68, DN_20K), /* GP_CAMERASB06 */
- PAD_NC(GPIO_69, DN_20K), /* GP_CAMERASB07 */
- PAD_NC(GPIO_70, DN_20K), /* GP_CAMERASB08 */
- PAD_NC(GPIO_71, DN_20K), /* GP_CAMERASB09 */
- PAD_NC(GPIO_72, DN_20K), /* GP_CAMERASB10 */
- PAD_NC(GPIO_73, DN_20K), /* GP_CAMERASB11 */
- /** End of North Community */
-};
-
-#endif
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c
deleted file mode 100644
index 6ec5b98..0000000
--- a/src/mainboard/intel/amenia/mainboard.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <soc/nhlt.h>
-#include "ec.h"
-#include "gpio.h"
-
-static void mainboard_init(void *chip_info)
-{
- gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
- mainboard_ec_init();
-}
-
-static unsigned long mainboard_write_acpi_tables(
- device_t device, unsigned long current, acpi_rsdp_t *rsdp)
-{
- uintptr_t start_addr;
- uintptr_t end_addr;
- struct nhlt *nhlt;
-
- start_addr = current;
-
- nhlt = nhlt_init();
-
- if (nhlt == NULL)
- return start_addr;
-
- /* 2 Channel DMIC array. */
- if (!nhlt_soc_add_dmic_array(nhlt, 2))
- printk(BIOS_ERR, "Added 2CH DMIC array.\n");
-
- /* Dialog for Headset codec.
- * Headset codec is bi-directional but uses the same configuration
- * settings for render and capture endpoints.
- */
- if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
- printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
-
- /* MAXIM Smart Amps for left and right speakers. */
- if (!nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP5))
- printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
-
- end_addr = nhlt_soc_serialize(nhlt, start_addr);
-
- if (end_addr != start_addr)
- acpi_add_table(rsdp, (void *)start_addr);
-
- return end_addr;
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
-}
-
-struct chip_operations mainboard_ops = {
- .init = mainboard_init,
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/intel/amenia/on_board.h b/src/mainboard/intel/amenia/on_board.h
deleted file mode 100644
index ab9bba3..0000000
--- a/src/mainboard/intel/amenia/on_board.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-*/
-
-#ifndef _ON_BOARD_H_
-#define _ON_BOARD_H_
-
-#include <soc/gpio_defs.h>
-
-#define TOUCHPAD_INT GPIO_18_IRQ
-#define TOUCHSCREEN_INT GPIO_21_IRQ
-
-
-#endif /* _ON_BOARD_H_ */
diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c
deleted file mode 100644
index 582c754..0000000
--- a/src/mainboard/intel/amenia/romstage.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/romstage.h>
-#include <string.h>
-#include <fsp/soc_binding.h>
-
-/* Channel 0 PHY to DUnit DQ mapping */
-static const uint8_t swizzling_ch0_amenia[] = {
- 9, 14, 12, 13, 10, 11, 8, 15, 7, 3, 5, 2, 6, 0, 1, 4,
- 28, 24, 26, 27, 29, 30, 31, 25, 20, 22, 23, 16, 19, 17, 18, 21,
-};
-
-/* Channel 1 PHY to DUnit DQ mapping */
-static const uint8_t swizzling_ch1_amenia[] = {
- 6, 7, 5, 4, 3, 1, 0, 2, 12, 10, 11, 13, 14, 8, 9, 15,
- 16, 22, 23, 20, 18, 17, 19, 21, 30, 28, 29, 25, 24, 26, 27, 31,
-};
-
-/* Channel 2 PHY to DUnit DQ mapping */
-static const uint8_t swizzling_ch2_amenia[] = {
- 15, 9, 8, 11, 14, 13, 12, 10, 4, 3, 7, 5, 6, 1, 0, 2,
- 25, 28, 30, 31, 26, 27, 24, 29, 20, 23, 22, 21, 18, 19, 16, 17,
-};
-
-/* Channel 3 PHY to DUnit DQ mapping */
-static const uint8_t swizzling_ch3_amenia[] = {
- 2, 1, 6, 7, 5, 4, 3, 0, 11, 10, 8, 9, 12, 15, 13, 14,
- 17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30,
-};
-
-static void amenia_fill_memory_params(FSP_M_CONFIG *cfg)
-{
- cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */
- cfg->DIMM0SPDAddress = 0;
- cfg->DIMM1SPDAddress = 0;
- cfg->Ch0_RankEnable = 0x1;
- cfg->Ch0_DeviceWidth = 0x1;
- cfg->Ch0_DramDensity = 0x2;
- cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
- cfg->Ch0_TristateClk1 = 0;
- cfg->Ch0_Mode2N = 0;
- cfg->Ch0_OdtLevels = 0;
- cfg->Ch1_RankEnable = 0x1;
- cfg->Ch1_DeviceWidth = 0x1;
- cfg->Ch1_DramDensity = 0x2;
- cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
- cfg->Ch1_TristateClk1 = 0;
- cfg->Ch1_Mode2N = 0;
- cfg->Ch1_OdtLevels = 0;
- cfg->Ch2_RankEnable = 0x1;
- cfg->Ch2_DeviceWidth = 0x1;
- cfg->Ch2_DramDensity = 0x2;
- cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
- cfg->Ch2_TristateClk1 = 0;
- cfg->Ch2_Mode2N = 0;
- cfg->Ch2_OdtLevels = 0;
- cfg->Ch3_RankEnable = 0x1;
- cfg->Ch3_DeviceWidth = 0x1;
- cfg->Ch3_DramDensity = 0x2;
- cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
- cfg->Ch3_TristateClk1 = 0;
- cfg->Ch3_Mode2N = 0;
- cfg->Ch3_OdtLevels = 0;
-
- memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_amenia,
- sizeof(swizzling_ch0_amenia));
- memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_amenia,
- sizeof(swizzling_ch1_amenia));
- memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_amenia,
- sizeof(swizzling_ch2_amenia));
- memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_amenia,
- sizeof(swizzling_ch3_amenia));
-}
-
-void mainboard_memory_init_params(FSPM_UPD *memupd)
-{
- FSP_M_CONFIG *cfg = &memupd->FspmConfig;
-
- cfg->Package = 1; /* 0x1:BGA */
- cfg->MemoryDown = 1;
- cfg->DDR3LPageSize = 0;
- cfg->DDR3LASR = 0;
- cfg->ScramblerSupport = 1;
- cfg->ChannelHashMask = 0x36;
- cfg->SliceHashMask = 0x9;
- cfg->InterleavedMode = 2;
- cfg->ChannelsSlicesEnable = 0;
- cfg->MinRefRate2xEnable = 0;
- cfg->DualRankSupportEnable = 1;
- cfg->DisableFastBoot = 0;
- cfg->RmtMode = 0;
- cfg->RmtCheckRun = 0;
- cfg->RmtMarginCheckScaleHighThreshold = 0;
- cfg->MemorySizeLimit = 0x1800; /* Limit to 6GB */
- cfg->LowMemoryMaxValue = 0;
- cfg->HighMemoryMaxValue = 0;
-
- amenia_fill_memory_params(cfg);
-}
diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c
deleted file mode 100644
index eb5377b..0000000
--- a/src/mainboard/intel/amenia/smihandler.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-#include <ec/google/chromeec/smm.h>
-#include <soc/pm.h>
-#include "ec.h"
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
- MAINBOARD_EC_S5_WAKE_EVENTS);
-}
-
-int mainboard_smi_apmc(u8 apmc)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
- MAINBOARD_EC_SMI_EVENTS);
- return 0;
-}
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