[coreboot-gerrit] New patch to review for coreboot: mainboard/gigabyte/ga-b75m-d3v/romstage.c: Use tabs for indents

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16816

-gerrit

commit eece372c4c775e5e550bae7393721ebb8eb82300
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Thu Sep 29 19:48:44 2016 +0200

    mainboard/gigabyte/ga-b75m-d3v/romstage.c: Use tabs for indents
    
    Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 42 +++++++++++++--------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index fcdac6d..83a53d0 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -82,10 +82,10 @@ void pch_enable_lpc(void)
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
 			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
 
-        pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
-        pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
 
-        pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+	pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
 
 	/* Initialize SuperIO */
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -93,27 +93,27 @@ void pch_enable_lpc(void)
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
-        { 1, 5, 0 },
-        { 1, 5, 0 },
-        { 1, 5, 1 },
-        { 1, 5, 1 },
-        { 1, 5, 2 },
-        { 1, 5, 2 },
-        { 1, 5, 3 },
-        { 1, 5, 3 },
-        { 1, 5, 4 },
-        { 1, 5, 4 },
-        { 1, 5, 6 },
-        { 1, 5, 5 },
-        { 1, 5, 5 },
-        { 1, 5, 6 },
+	{ 1, 5, 0 },
+	{ 1, 5, 0 },
+	{ 1, 5, 1 },
+	{ 1, 5, 1 },
+	{ 1, 5, 2 },
+	{ 1, 5, 2 },
+	{ 1, 5, 3 },
+	{ 1, 5, 3 },
+	{ 1, 5, 4 },
+	{ 1, 5, 4 },
+	{ 1, 5, 6 },
+	{ 1, 5, 5 },
+	{ 1, 5, 5 },
+	{ 1, 5, 6 },
 };
 
 void mainboard_get_spd(spd_raw_data *spd) {
-        read_spd (&spd[0], 0x50);
-        read_spd (&spd[1], 0x51);
-        read_spd (&spd[2], 0x52);
-        read_spd (&spd[3], 0x53);
+	read_spd (&spd[0], 0x50);
+	read_spd (&spd[1], 0x51);
+	read_spd (&spd[2], 0x52);
+	read_spd (&spd[3], 0x53);
 }
 
 void mainboard_early_init(int s3resume) {