[coreboot-gerrit] New patch to review for coreboot: nb/gm45: allow use of 352M preallocated ram for igd
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Fri Sep 30 21:30:57 CEST 2016
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16831
-gerrit
commit dcbece878f8aab282ccb817a3e9a096e503be3df
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Fri Sep 30 21:03:23 2016 +0200
nb/gm45: allow use of 352M preallocated ram for igd
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family"
mention the possibility of having 352M ram preallocated for the
integrated graphic device. This only worked fine if the amount of ram in
the system was 3GB or less. When 4G or more is installed, memory is
remapped to create a 1GB large pci mmio hole which is not enough and
creates conflicts when 352M vram is used.
This patch increases the pci mmio hole size on Lenovo x200 to allow
352M vram to work.
Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/mainboard/lenovo/t400/cmos.layout | 1 +
src/mainboard/lenovo/x200/cmos.layout | 1 +
src/mainboard/lenovo/x200/devicetree.cb | 2 +-
src/mainboard/roda/rk9/cmos.layout | 1 +
src/northbridge/intel/gm45/igd.c | 2 +-
5 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
index d62042c..61212dd 100644
--- a/src/mainboard/lenovo/t400/cmos.layout
+++ b/src/mainboard/lenovo/t400/cmos.layout
@@ -139,6 +139,7 @@ enumerations
11 9 96M
11 10 160M
11 11 224M
+11 12 352M
12 0 Integrated Only
12 1 Discrete Only
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
index 19ead05..35d5017 100644
--- a/src/mainboard/lenovo/x200/cmos.layout
+++ b/src/mainboard/lenovo/x200/cmos.layout
@@ -136,6 +136,7 @@ enumerations
11 9 96M
11 10 160M
11 11 224M
+11 12 352M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 200b4bc..d9cb783 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/intel/gm45
end
end
- register "pci_mmio_size" = "1024"
+ register "pci_mmio_size" = "2048"
device domain 0 on
device pci 00.0 on
diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout
index 711551b..d9119b3 100644
--- a/src/mainboard/roda/rk9/cmos.layout
+++ b/src/mainboard/roda/rk9/cmos.layout
@@ -124,6 +124,7 @@ enumerations
11 9 96M
11 10 160M
11 11 224M
+11 12 352M
# -----------------------------------------------------------------
checksums
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 73f7651..74572ca 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -157,7 +157,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
gfxsize = 4;
}
/* Handle invalid cmos settings */
- if (gfxsize > 11)
+ if (gfxsize > 12)
gfxsize = 4;
sysinfo->ggc = 0x0300 | ((gfxsize + 1) << 4);
if (!(capid & (1 << (48 - 32))))
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