[coreboot-gerrit] New patch to review for coreboot: [WIP]soc/intel/apollolake:Implement stage cache to improve resume time
Brandon Breitenstein (brandon.breitenstein@intel.com)
gerrit at coreboot.org
Fri Sep 30 23:36:34 CEST 2016
Brandon Breitenstein (brandon.breitenstein at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833
-gerrit
commit ecce49e0f88046e21ec45a71e6d9b8771badb1c4
Author: Brandon Breitenstein <brandon.breitenstein at intel.com>
Date: Fri Sep 30 13:57:12 2016 -0700
[WIP]soc/intel/apollolake:Implement stage cache to improve resume time
This patch enables stage cache to save some time during resume.
It saves ramstage in the stage cache and restores it on resume
so that it does not have to reinitialize ramstage during the
resume flow. Currently the stage cache is being lost on S3
entrance with this patch and it is being debugged.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=work in progress
Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Signed-off-by: Brandon Breitenstein <brandon.breitenstein at intel.com>
---
src/soc/intel/apollolake/Kconfig | 3 ++-
src/soc/intel/apollolake/cpu.c | 13 +++++++++++--
src/soc/intel/apollolake/include/soc/smm.h | 4 +---
src/soc/intel/apollolake/memmap.c | 30 ++++++++++++++++++++++++++++++
src/soc/intel/apollolake/romstage.c | 19 +++++++++++++++++++
5 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 3a23dbd..4f3f29f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_NHLT
# Misc options
select C_ENVIRONMENT_BOOTBLOCK
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select COMMON_FADT
select GENERIC_GPIO_LIB
@@ -34,7 +35,7 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
- select NO_STAGE_CACHE
+ # select NO_STAGE_CACHE
select NO_XIP_EARLY_STAGES
select PARALLEL_MP
select PCIEXP_ASPM
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 86fe3e1..c4893e5 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -47,6 +47,8 @@ static const struct cpu_driver driver __cpu_driver = {
* MP and SMM loading initialization.
*/
struct smm_relocation_attrs {
+ uint32_t smram_base;
+ uint32_t smram_size;
uint32_t smbase;
uint32_t smrr_base;
uint32_t smrr_mask;
@@ -99,19 +101,26 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
{
void *smm_base;
size_t smm_size;
+ void *handler_base;
+ size_t handler_size;
/* All range registers are aligned to 4KiB */
const uint32_t rmask = ~((1 << 12) - 1);
/* Initialize global tracking state. */
smm_region(&smm_base, &smm_size);
+ smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
+
+ relo_attrs.smram_size = handler_size;
+ relo_attrs.smram_base = (uint32_t)handler_base;
+
relo_attrs.smbase = (uint32_t)smm_base;
relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
- *perm_smbase = relo_attrs.smbase;
- *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE;
+ *perm_smbase = relo_attrs.smram_base;
+ *perm_smsize = relo_attrs.smram_size;
*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
}
diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h
index 7a9846e..740d02b 100644
--- a/src/soc/intel/apollolake/include/soc/smm.h
+++ b/src/soc/intel/apollolake/include/soc/smm.h
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <soc/gpio.h>
+#include <fsp/memmap.h>
/* These helpers are for performing SMM relocation. */
void southbridge_clear_smi_status(void);
@@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void);
/* Mainboard handler for GPI SMIs*/
void mainboard_smi_gpi_handler(const struct gpi_status *sts);
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
#endif
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index ea6f447..60d918c 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -52,3 +52,33 @@ void smm_region(void **start, size_t *size)
*start = (void *)smm_region_start();
*size = smm_region_size();
}
+
+int smm_subregion(int sub, void **start, size_t *size)
+{
+ uintptr_t sub_base;
+ size_t sub_size;
+ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+ sub_base = smm_region_start();
+ sub_size = smm_region_size();
+
+ switch (sub) {
+ case SMM_SUBREGION_HANDLER:
+ /* Handler starts at the base of TSEG. */
+ sub_size -= cache_size;
+ break;
+ case SMM_SUBREGION_CACHE:
+ /* External cache is in the middle of TSEG. */
+ sub_base += sub_size - cache_size;
+ sub_size = cache_size;
+ break;
+ default:
+ return -1;
+ }
+
+ *start = (void *)sub_base;
+ *size = sub_size;
+
+ return 0;
+}
+
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index b9733de..328ed6d 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -29,6 +29,7 @@
#include <device/pci_def.h>
#include <device/resource.h>
#include <fsp/api.h>
+#include <fsp/memmap.h>
#include <fsp/util.h>
#include <soc/iomap.h>
#include <soc/northbridge.h>
@@ -135,6 +136,24 @@ asmlinkage void car_stage_entry(void)
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
MTRR_TYPE_WRPROT);
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ void *smm_base;
+ size_t smm_size;
+ uintptr_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uintptr_t)smm_base;
+ postcar_frame_add_mtrr(&pcf, tseg_base, smm_size,
+ MTRR_TYPE_WRBACK);
+ }
+
run_postcar_phase(&pcf);
}
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