[coreboot-gerrit] Patch set updated for coreboot: mb/google/poppy: Enable dptf
Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)
gerrit at coreboot.org
Fri Jan 13 15:58:13 CET 2017
Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17926
-gerrit
commit cb47ed3181d4a4baf36a3bd2a3d99d629ed88dfb
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date: Fri Jan 13 20:05:16 2017 +0530
mb/google/poppy: Enable dptf
DPTF Participants:
1. B0D4
2. Battery Charger
Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
src/mainboard/google/poppy/acpi/dptf.asl | 58 ++++++++++++++++++++++++++++++++
src/mainboard/google/poppy/devicetree.cb | 4 +++
src/mainboard/google/poppy/dsdt.asl | 3 ++
3 files changed, 65 insertions(+)
diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl
new file mode 100644
index 0000000..3fba587
--- /dev/null
+++ b/src/mainboard/google/poppy/acpi/dptf.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 94
+#define DPTF_CPU_CRITICAL 99
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 4500, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 3000, /* PowerLimitMinimum */
+ 7000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 4283a34..481900c 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -19,6 +19,9 @@ chip soc/intel/skylake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
@@ -184,6 +187,7 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
register "tdp_pl2_override" = "7"
+ register "tcc_offset" = "10" # TCC of 90C
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index c678dfc..ed97848 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -45,6 +45,9 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
}
/* Chrome OS specific */
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