[coreboot-gerrit] New patch to review for coreboot: [NOTFORMERGE] binaryPI: Redo CAR teardown with empty stack
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Mar 1 12:50:20 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18525
-gerrit
commit e307fe36db57bec69e33bfd86919a46caa449e21
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Feb 26 11:33:05 2017 +0200
[NOTFORMERGE] binaryPI: Redo CAR teardown with empty stack
This is squashed set of commits for amd/agesa/cache_as_ram.inc
that have not yet landed.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/pi/cache_as_ram.inc | 92 +++++++++++++++++------------------------
1 file changed, 37 insertions(+), 55 deletions(-)
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index 24db600..f43e6a4 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -26,43 +26,24 @@
#include "gcccar.inc"
#include <cpu/x86/cache.h>
-/*
- * XMM map:
- * xmm0: BIST
- * xmm1: backup ebx -- cpu_init_detected
- */
-
.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+.globl cache_as_ram_setup, cache_as_ram_setup_out
cache_as_ram_setup:
- post_code(0xa0)
-
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3<<9), %eax
- movl %eax, %cr4
-
- /* Get the cpu_init_detected */
- mov $1, %eax
- cpuid
- shr $24, %ebx
-
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
- /* for normal part %ebx already contain cpu_init_detected from fallback call */
+ /* Preserve BIST. */
+ movl %eax, %ebp
- /* Save the cpu_init_detected */
- cvtsi2sd %ebx, %xmm1
+ post_code(0xa0)
post_code(0xa1)
+ /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
AMD_ENABLE_STACK
+ /* Align the stack to 128 bits. No harm on i386, required on x86_64? */
+ and $0xFFFFFFF0, %esp
+
#ifdef __x86_64__
/* switch to 64 bit long mode */
mov %esi, %ecx
@@ -105,42 +86,36 @@ cache_as_ram_setup:
# use call far to switch to 64-bit code segment
ljmp $0x18, $1f
1:
- /* Pass the cpu_init_detected */
- cvtsd2si %xmm1, %esi
- /* Pass the BIST result */
- cvtsd2si %xmm0, %edi
+ .code64
+
+ /* Calling conventions preserve BIST in %ebp. */
- /* align the stack */
- and $0xFFFFFFF0, %esp
+ call early_all_cores
+
+ movl %ebp, %edi
+ call romstage_main
+ movl %eax, %ebx
- .code64
- call cache_as_ram_main
.code32
#else
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
+ /* Calling conventions preserve BIST in %ebp. */
- /* Restore the cpu_init_detected */
- cvtsd2si %xmm1, %ebx
+ call early_all_cores
+
+ pushl %ebp
+ call romstage_main
+ movl %eax, %ebx
- pushl %ebx /* init detected */
- pushl %edx /* bist */
- call cache_as_ram_main
#endif
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
+/* Register %ebx is new stacktop for remaining of romstage.
+ * It is the only register preserved in AMD_DISABLE_STACK.
+ */
disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
/* Disable cache */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
@@ -152,13 +127,20 @@ disable_cache_as_ram:
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
- xorl %eax, %eax
- /* Restore the return stack */
wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
+
+#ifdef __x86_64__
+.code64
+#endif
+
+ movl %ebx, %esp
+ call romstage_after_car
+
+ /* Should never see this postcode */
+ post_code(0xaf)
+stop:
+ jmp stop
cache_as_ram_setup_out:
#ifdef __x86_64__
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