[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Add option to indicate voltage margining enabled/disabled
Rizwan Qureshi (rizwan.qureshi@intel.com)
gerrit at coreboot.org
Wed Mar 1 18:37:50 CET 2017
Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469
-gerrit
commit 0d8b304e1657e7f27852334f9684fd84531b868f
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date: Thu Feb 23 14:43:39 2017 +0530
soc/intel/skylake: Add option to indicate voltage margining enabled/disabled
Support for voltage margining is dependent on the platform. Enbaling voltage
margining puts additional constraints for the SLP_S0# to be asserted and hence
moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
src/soc/intel/skylake/chip.h | 8 ++++++++
src/soc/intel/skylake/chip_fsp20.c | 5 +++++
2 files changed, 13 insertions(+)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 2e4adb2..8e6fa69 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -333,6 +333,14 @@ struct soc_intel_skylake_config {
* Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
*/
u8 PmConfigPwrBtnOverridePeriod;
+
+ /*
+ * PCH Pm Slp S0 Voltage Margining Enable
+ * Indicates platform has support for VCCPrim_Core Voltage Margining
+ * in SLP_S0# asserted state.
+ */
+ u8 PchPmSlpS0VmEnable;
+
/*
* Reset Power Cycle Duration could be customized in the unit of second.
* PCH HW default is 4 seconds, and range is 1~4 seconds.
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 8b8c37c..3d2f2cb 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -220,6 +220,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod;
params->PchPmPwrCycDur = config->PmConfigPwrCycDur;
+
+ /* Disable Voltage margining if S0ix is enabled */
+ if (config->s0ix_enable)
+ params->PchPmSlpS0VmEnable = 0x0;
+
params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
params->PchSirqMode = config->SerialIrqConfigSirqMode;
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