[coreboot-gerrit] Patch set updated for coreboot: soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP]
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Fri Mar 3 21:41:45 CET 2017
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18449
-gerrit
commit 32549bfb1c4e453a06dd89b4d32c291e6f7331de
Author: Subrata Banik <subrata.banik at intel.com>
Date: Wed Feb 22 15:01:26 2017 +0530
soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP]
Copied from APL latest git.
Change-Id: Icf1bb95cd2503e12f8ce26d77d2cd940a2ea1b69
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/glk/Kconfig | 233 +++++++++++++++++++++++++++++++++++++++++
src/soc/intel/glk/Makefile.inc | 40 +++++++
2 files changed, 273 insertions(+)
diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig
new file mode 100644
index 0000000..9e843d8
--- /dev/null
+++ b/src/soc/intel/glk/Kconfig
@@ -0,0 +1,233 @@
+config SOC_INTEL_GLK
+ bool
+ help
+ Intel GLK support
+
+if SOC_INTEL_GLK
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select BOOTBLOCK_CONSOLE
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
+ select BOOT_DEVICE_SUPPORTS_WRITES
+ # CPU specific options
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select IOAPIC
+ select SMP
+ select SSE2
+ select SUPPORT_CPU_UCODE_IN_CBFS
+ # Audio options
+ select ACPI_NHLT
+ select SOC_INTEL_COMMON_NHLT
+ # Misc options
+ select C_ENVIRONMENT_BOOTBLOCK
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+ select COLLECT_TIMESTAMPS
+ select COMMON_FADT
+ select GENERIC_GPIO_LIB
+ select HAVE_INTEL_FIRMWARE
+ select HAVE_SMI_HANDLER
+ select MRC_SETTINGS_PROTECT
+ select NO_FIXED_XIP_ROM_SIZE
+ select NO_XIP_EARLY_STAGES
+ select PARALLEL_MP
+ select PARALLEL_MP_AP_WORK
+ select PCIEXP_ASPM
+ select PCIEXP_COMMON_CLOCK
+ select PCIEXP_CLK_PM
+ select PCIEXP_L1_SUB_STATE
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
+ select REG_SCRIPT
+ select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
+ select RTC
+ select SMM_TSEG
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_ACPI
+ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_LPSS_I2C
+ select SOC_INTEL_COMMON_SMI
+ select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
+ select HAVE_MONOTONIC_TIMER
+ select PLATFORM_USES_FSP2_0
+ select HAVE_HARD_RESET
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_GFX_OPREGION
+ select ADD_VBT_DATA_FILE
+
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+ select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
+ select SEPARATE_VERSTAGE
+ select VBOOT_OPROM_MATTERS
+ select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+ select VIRTUAL_DEV_SWITCH
+
+config TPM_ON_FAST_SPI
+ bool
+ default n
+ select LPC_TPM
+ help
+ TPM part is conntected on Fast SPI interface, but the LPC MMIO
+ TPM transactions are decoded and serialized over the SPI interface.
+
+config SOC_INTEL_COMMON_RESET
+ bool
+ default y
+
+config MMCONF_BASE_ADDRESS
+ hex "PCI MMIO Base Address"
+ default 0xe0000000
+
+config IOSF_BASE_ADDRESS
+ hex "MMIO Base Address of sideband bus"
+ default 0xd0000000
+
+config DCACHE_RAM_BASE
+ hex "Base address of cache-as-RAM"
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ hex "Length in bytes of cache-as-RAM"
+ default 0xc0000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
+ depends on SOC_INTEL_COMMON_LPSS_I2C
+ int
+ default 133
+
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
+config SOC_UART_DEBUG
+ bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
+ default n
+ select CONSOLE_SERIAL
+ select DRIVERS_UART
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+
+# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
+config C_ENV_BOOTBLOCK_SIZE
+ hex
+ default 0x8000
+
+# This SoC does not map SPI flash like many previous SoC. Therefore we provide
+# a custom media driver that facilitates mapping
+config X86_TOP4G_BOOTMEDIA_MAP
+ bool
+ default n
+
+config ROMSTAGE_ADDR
+ hex
+ default 0xfef20000
+ help
+ The base address (in CAR) where romstage should be linked
+
+config VERSTAGE_ADDR
+ hex
+ default 0xfef40000
+ help
+ The base address (in CAR) where verstage should be linked
+
+config CACHE_MRC_SETTINGS
+ bool
+ default y
+
+config MRC_SETTINGS_VARIABLE_DATA
+ bool
+ default y
+
+config FSP_M_ADDR
+ hex
+ default 0xfef40000
+ help
+ The address FSP-M will be relocated to during build time
+
+config NEED_LBP2
+ bool "Write contents for logical boot partition 2."
+ default n
+ help
+ Write the contents from a file into the logical boot partition 2
+ region defined by LBP2_FMAP_NAME.
+
+config LBP2_FMAP_NAME
+ string "Name of FMAP region to put logical boot partition 2"
+ depends on NEED_LBP2
+ default "SIGN_CSE"
+ help
+ Name of FMAP region to write logical boot partition 2 data.
+
+config LBP2_FILE_NAME
+ string "Path of file to write to logical boot partition 2 region"
+ depends on NEED_LBP2
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin"
+ help
+ Name of file to store in the logical boot partition 2 region.
+
+config NEED_IFWI
+ bool "Write content into IFWI region"
+ default n
+ help
+ Write the content from a file into IFWI region defined by
+ IFWI_FMAP_NAME.
+
+config IFWI_FMAP_NAME
+ string "Name of FMAP region to pull IFWI into"
+ depends on NEED_IFWI
+ default "IFWI"
+ help
+ Name of FMAP region to write IFWI.
+
+config IFWI_FILE_NAME
+ string "Path of file to write to IFWI region"
+ depends on NEED_IFWI
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
+ help
+ Name of file to store in the IFWI region.
+
+config HEAP_SIZE
+ hex
+ default 0x8000
+
+config SPI_FLASH_INCLUDE_ALL_DRIVERS
+ bool
+ default n
+
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
+config IFD_CHIPSET
+ string
+ default "aplk"
+
+endif
diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc
new file mode 100644
index 0000000..92c3bc2
--- /dev/null
+++ b/src/soc/intel/glk/Makefile.inc
@@ -0,0 +1,40 @@
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+
+subdirs-y += ../../../cpu/intel/microcode
+subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../cpu/x86/lapic
+subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/smm
+subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/x86/cache
+
+CPPFLAGS_common += -I$(src)/soc/intel/glk/include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
+
+# Since FSP-M runs in CAR we need to relocate it to a specific address
+$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
+
+ifeq ($(CONFIG_NEED_LBP2),y)
+files_added::
+ $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward
+endif
+
+# Bootblock on GLK platform lies in the IFWI region. In order to place
+# the bootblock at the right location in IFWI image -
+# a. Using ifwitool:
+# 1. Create IFWI image (ifwi.bin.tmp) from input image
+# (CONFIG_IFWI_FILE_NAME).
+# 2. Delete OBBP sub-partition, if present.
+# 3. Replace IBBL directory entry in IBBP sub-partition with currently
+# generated bootblock.bin.
+# b. Using cbfstool:
+# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME.
+ifeq ($(CONFIG_NEED_IFWI),y)
+files_added:: $(IFWITOOL)
+ $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp
+ $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP
+ $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL
+ $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward
+endif
+
+endif
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