[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Fix errors detected by checkpatch
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Mon Mar 6 18:15:37 CET 2017
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18591
-gerrit
commit 47a3890fbca4964b03c55de775e2130c8d39c771
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Mon Mar 6 08:59:23 2017 -0800
soc/intel/quark: Fix errors detected by checkpatch
Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/bootblock/bootblock.c | 4 +-
src/soc/intel/quark/chip.h | 6 +-
src/soc/intel/quark/include/soc/IntelQNCConfig.h | 14 +-
src/soc/intel/quark/include/soc/Ioh.h | 49 +--
src/soc/intel/quark/include/soc/QuarkNcSocId.h | 443 ++++++++++++-----------
src/soc/intel/quark/include/soc/pci_devs.h | 4 +-
src/soc/intel/quark/include/soc/reg_access.h | 5 +-
src/soc/intel/quark/lpc.c | 4 +-
src/soc/intel/quark/reg_access.c | 22 +-
src/soc/intel/quark/romstage/fsp2_0.c | 5 +-
10 files changed, 299 insertions(+), 257 deletions(-)
diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
index c974cb1..2bcc3f0 100644
--- a/src/soc/intel/quark/bootblock/bootblock.c
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -77,7 +77,7 @@ static const struct reg_script mtrr_init[] = {
REG_SCRIPT_END
};
-void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
light_sd_led();
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index b239631..25d734a 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -41,7 +41,7 @@ struct soc_intel_quark_config {
* MemoryInit:
*
* The following fields come from FspUpdVpd.h and are defined as PCDs
- * for the FSP binary. Data for these fields comes from the board's
+ * for the FSP binary. Data for these fields comes from the board's
* devicetree.cb file which gets processed into static.c and then
* built into the coreboot image. The fields below contain retain
* the FSP PCD field name.
@@ -90,7 +90,7 @@ struct soc_intel_quark_config {
* impedance control.
*/
uint8_t DramRonVal;
- uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
+ uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */
uint8_t DramRttWrVal; /* 0=off others=RESERVED */
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
diff --git a/src/soc/intel/quark/include/soc/IntelQNCConfig.h b/src/soc/intel/quark/include/soc/IntelQNCConfig.h
index 91757e6..d13f9dc 100644
--- a/src/soc/intel/quark/include/soc/IntelQNCConfig.h
+++ b/src/soc/intel/quark/include/soc/IntelQNCConfig.h
@@ -1,7 +1,7 @@
/** @file
Some configuration of QNC Package
-Copyright (c) 2013-2015 Intel Corporation.
+Copyright (c) 2013-2017 Intel Corporation.
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License. The full text of the license
@@ -23,11 +23,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
// Memory arbiter fixed config values.
//
#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
- (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
- (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
- (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
- (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
- ))
+ (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
+ (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
+ (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
+ (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
+ ))
//
// Memory Manager fixed config values.
@@ -67,6 +67,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// PCIe Root Port fixed config values.
//
-#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
+#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
#endif
diff --git a/src/soc/intel/quark/include/soc/Ioh.h b/src/soc/intel/quark/include/soc/Ioh.h
index 308bf8c..521ae83 100644
--- a/src/soc/intel/quark/include/soc/Ioh.h
+++ b/src/soc/intel/quark/include/soc/Ioh.h
@@ -1,17 +1,16 @@
/** @file
-Header file for QuarkSCSocId Ioh.
-Copyright (c) 2013-2015 Intel Corporation.
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-
-**/
+ * Header file for QuarkSCSocId Ioh.
+ * Copyright (c) 2013-2017 Intel Corporation.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ */
#ifndef _IOH_H_
#define _IOH_H_
@@ -60,9 +59,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define BIT31 0x80000000
#endif
-#define IOH_PCI_CFG_ADDRESS(bus,dev,func,reg) \
- ((UINT32) ( (((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
- (((UINTN)func) << 8) + ((UINTN)reg) ))& 0x00000000ffffffff
+#define IOH_PCI_CFG_ADDRESS(bus, dev, func, reg) \
+ (((UINT32) ((((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
+ (((UINTN)func) << 8) + ((UINTN)reg))) & 0x00000000ffffffff)
//----------------------------------------------------------------------------
@@ -156,9 +155,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define R_IOH_EHCI_CAPLENGTH 0x00
#define R_IOH_EHCI_INSNREG01 0x94
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)
-#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
+#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK \
+ (0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)
-#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
+#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK \
+ (0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
//
// EHCI memory mapped registers offset from memory BAR0 + Cap length value.
@@ -185,12 +186,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//---------------------------------------------------------------------------
// Quark South Cluster 10/100 Mbps Ethernet Device definitions.
//---------------------------------------------------------------------------
-#define IOH_MAC0_BUS_NUMBER IOH_BUS
-#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
-#define IOH_MAC0_FUNCTION_NUMBER 0x06
-#define IOH_MAC1_BUS_NUMBER IOH_BUS
-#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
-#define IOH_MAC1_FUNCTION_NUMBER 0x07
+#define IOH_MAC0_BUS_NUMBER IOH_BUS
+#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
+#define IOH_MAC0_FUNCTION_NUMBER 0x06
+#define IOH_MAC1_BUS_NUMBER IOH_BUS
+#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
+#define IOH_MAC1_FUNCTION_NUMBER 0x07
//
// MAC Device PCI config registers.
diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
index 8b5ca2c..21dc7f8 100644
--- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h
+++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
@@ -1,7 +1,7 @@
/** @file
QuarkNcSocId Register Definitions
-Copyright (c) 2013-2015 Intel Corporation.
+Copyright (c) 2013-2017 Intel Corporation.
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License. The full text of the license
@@ -12,7 +12,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
-Definitions beginning with "V_" are meaningful values of bits within the registers
+Definitions beginning with "V_" are meaningful values of bits within registers
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
@@ -84,7 +84,7 @@ Definitions beginning with "N_" are the bit position
// [ 7:4 ] Message write byte enable : F is enable
// [ 3:0 ] Reserved
//
-#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register
+#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register
// Always Set to 0xF0
#define QNC_MCR_MASK 0x000000ff
#define QNC_MCR_BYTE_ENABLES 0x000000f0
@@ -97,12 +97,12 @@ Definitions beginning with "N_" are the bit position
//
//MEA - B0:D0:F0:RD8h (RW)- Message extended address register
//
-#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register
+#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Addr reg
#define QNC_MEA_MASK 0xffffff00
-#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR
-#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR
-#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR
+#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR
+#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR
+#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR
//
// Misc Useful Macros
@@ -113,26 +113,27 @@ Definitions beginning with "N_" are the bit position
//
// QNC Message OpCodes and Attributes
//
-#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode
-#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode
+#define QUARK_OPCODE_READ 0x10 // Message bus "read" opcode
+#define QUARK_OPCODE_WRITE 0x11 // Message bus "write" opcode
//
// Alternative opcodes for the SCSS block
//
-#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode
-#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode
+#define QUARK_ALT_OPCODE_READ 0x06 // Message bus "read" opcode
+#define QUARK_ALT_OPCODE_WRITE 0x07 // Message bus "write" opcode
//
// QNC Message OpCodes and Attributes for IO
//
-#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode
-#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode
+#define QUARK_OPCODE_IO_READ 0x02 // Message bus "IO read" opcode
+#define QUARK_OPCODE_IO_WRITE 0x03 // Message bus "IO write" opcode
-#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode
+#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Message bus "RMU Main binary
+ // shadow" opcode
-#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode
-#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode
+#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark RMU "scrub resume" opcode
+#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark RMU "scrub pause" opcode
//
// QNC Message Ports and Registers
@@ -153,11 +154,12 @@ Definitions beginning with "N_" are the bit position
//
// Quark Memory Arbiter Registers.
//
-#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register.
-#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient
-#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh.
-#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing.
-#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing.
+#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI
+ // Status encodings reg
+#define ASTATUS_PRI_CASUAL 0x0 // Service if convenient
+#define ASTATUS_PRI_IMPENDING 0x1 // DRAM is in Self-Refresh
+#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing
+#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing
#define ASTATUS1_RASISED_BP (10)
#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
#define ASTATUS0_RASISED_BP (8)
@@ -170,40 +172,44 @@ Definitions beginning with "N_" are the bit position
//
// Quark Memory Controller Registers.
//
-#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register.
+#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register
#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.
//
// Quark Remote Management Unit Registers.
//
-#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address
+#define QNC_MSG_TMPM_REG_PMBA 0x70 // PM I/O Base Address
-#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register.
+#define QUARK_NC_RMU_REG_CONFIG 0x71 // RMU configuration reg
#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)
#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)
-#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1.
+#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // RMU Options register 1
#define OPTIONS_1_DMA_DISABLE (BIT0)
-#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register.
+#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // RMU Watchdog control
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18
-#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
-#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
-#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
-#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
-
-#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register.
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE 0
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT \
+ (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM \
+ (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR \
+ (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
+
+#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // RMU Thermal sensor mode
#define TS_ENABLE (BIT15)
-#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register.
+#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // RMU Thermal sensor
+ // programmable trip point
#define TS_HOT_TRIP_CLEAR_THOLD_BP 24
-#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)
+#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)
#define TS_CAT_TRIP_CLEAR_THOLD_BP 16
-#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)
+#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)
#define TS_HOT_TRIP_SET_THOLD_BP 8
-#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)
+#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)
#define TS_CAT_TRIP_SET_THOLD_BP 0
-#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)
+#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)
#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50
#define SCRUB_CFG_INTERVAL_SHIFT 0x00
@@ -218,14 +224,14 @@ Definitions beginning with "N_" are the bit position
#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C
#define SCRUB_RESUME_MSG() ((UINT32)( \
- (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
- (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
- 0xF0))
+ (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
+ 0xF0))
#define SCRUB_PAUSE_MSG() ((UINT32)( \
- (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
- (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
- 0xF0))
+ (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
+ (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
+ 0xF0))
//
// Quark Memory Manager Registers
@@ -239,7 +245,7 @@ Definitions beginning with "N_" are the bit position
#define EnableSMMInt BIT31
#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20
#define DRAM_NON_HOST_RQ_LIMIT_BP 0
-#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)
+#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)
#define QUARK_NC_TOTAL_IMR_SET 0x8
#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40
@@ -250,42 +256,45 @@ Definitions beginning with "N_" are the bit position
#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54
#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58
#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C
- #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00
- #define IMR_LOCK BIT31
- #define IMR_EN BIT30
- #define IMRL_MASK 0x00FFFFFC
- #define IMRL_RESET 0x00000000
- #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01
- #define IMRH_MASK 0x00FFFFFC
- #define IMRH_RESET 0x00000000
- #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02
- #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03
- #define IMRX_ALL_ACCESS 0xFFFFFFFF
- #define CPU_SNOOP BIT30
- #define RMU BIT29
- #define CPU0_NON_SMM BIT0
+#define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00
+#define IMR_LOCK BIT31
+#define IMR_EN BIT30
+#define IMRL_MASK 0x00FFFFFC
+#define IMRL_RESET 0x00000000
+#define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01
+#define IMRH_MASK 0x00FFFFFC
+#define IMRH_RESET 0x00000000
+#define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02
+#define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03
+#define IMRX_ALL_ACCESS 0xFFFFFFFF
+#define CPU_SNOOP BIT30
+#define RMU BIT29
+#define CPU0_NON_SMM BIT0
//
// Quark Host Bridge Registers (Datasheet 12.7.2)
//
-#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls
-#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)
-#define FSEG_RD_DRAM (BIT2) // Enable RAM for 0x000f0000 - 0x000fffff
-#define ESEG_RD_DRAM (BIT1) // Enable RAM for 0x000e0000 - 0x000effff
-#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control
-#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
-#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN
-#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN
-#define SMM_CTL_EN (BIT3) // SMM enable
-#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN
-#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
-#define SMM_LOCKED (BIT0) // SMM Locked
+#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls
+#define SMI_EN (BIT19) // SMI Global Enable
+ // (from Legacy Bridge)
+#define FSEG_RD_DRAM (BIT2) // Enable RAM for 0xf0000
+ // - 0xfffff
+#define ESEG_RD_DRAM (BIT1) // Enable RAM for 0xe0000
+ // - 0xeffff
+#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control
+#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
+#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN
+#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN
+#define SMM_CTL_EN (BIT3) // SMM enable
+#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN
+#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
+#define SMM_LOCKED (BIT0) // SMM Locked
#define SMM_START_MASK 0x0000FFF0
#define SMM_END_MASK 0xFFF00000
-#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08
+#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08
#define HMBOUND_MASK 0x0FFFFF000
#define HMBOUND_LOCK BIT0
-#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A
+#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A
#define HLEGACY_SMI_PIN_VALUE BIT12
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41
@@ -330,7 +339,8 @@ Definitions beginning with "N_" are the bit position
#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3
-#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
+#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9\
+ | BIT8)
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8
#define B_TSCGF1_CONFIG_IBGEN BIT17
#define B_TSCGF1_CONFIG_IBGEN_BP 17
@@ -356,7 +366,8 @@ Definitions beginning with "N_" are the bit position
#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34
#define B_TSCGF3_CONFIG_ITSRST BIT0
#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11
-#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)
+#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK \
+ (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)
#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36
#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20
@@ -374,8 +385,13 @@ Definitions beginning with "N_" are the bit position
#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3
#define B_CFG_STICKY_RW_WARM_RST BIT4
#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9
-#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION)
-#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST)
+#define B_CFG_STICKY_RW_VIOLATION \
+ (B_CFG_STICKY_RW_SMM_VIOLATION \
+ | B_CFG_STICKY_RW_HMB_VIOLATION \
+ | B_CFG_STICKY_RW_IMR_VIOLATION \
+ | B_CFG_STICKY_RW_DECC_VIOLATION)
+#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION \
+ | B_CFG_STICKY_RW_WARM_RST)
//
// iCLK Registers.
@@ -425,7 +441,7 @@ Definitions beginning with "N_" are the bit position
// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h)
// Suggested Value for SMBA = 0x1040
//
-#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W
+#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W
#define B_QNC_SMBUS_START (BIT4) // Start/Stop
#define V_QNC_SMBUS_HCTL_CMD_QUICK 0
#define V_QNC_SMBUS_HCTL_CMD_BYTE 1
@@ -434,23 +450,24 @@ Definitions beginning with "N_" are the bit position
#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4
#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5
-#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W
+#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W
#define B_QNC_SMBUS_BERR (BIT2) // BUS Error
#define B_QNC_SMBUS_DERR (BIT1) // Device Error
#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status
#define B_QNC_SMBUS_HSTS_ALL 0x07
-#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W
+#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W
#define V_QNC_SMBUS_HCLK_100KHZ 0x0054
-#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
+#define R_QNC_SMBUS_TSA 0x04 // Tx Slave Address Register R/W
#define V_QNC_SMBUS_RW_SEL_READ 1
#define V_QNC_SMBUS_RW_SEL_WRITE 0
-#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W
-#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W
-#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W
-#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh
+#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W
+#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W
+#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W
+#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W
+ // [255:0] ~ 3Fh
#define R_QNC_LPC_GBA_BASE 0x44
#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0
@@ -461,21 +478,21 @@ Definitions beginning with "N_" are the bit position
#define R_QNC_GPIO_CGEN_CORE_WELL 0x00
#define R_QNC_GPIO_CGIO_CORE_WELL 0x04
#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08
-#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable
-#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable
-#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable
-#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable
-#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status
+#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // CW GPIO Trigger Pos Edge Enable
+#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // CW GPIO Trigger Neg Edge Enable
+#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable
+#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable
+#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status
#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20
#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24
#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28
-#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable
-#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable
-#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable
-#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable
-#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status
-#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable
-#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable
+#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // RW GPIO Trigger Pos Edge Enable
+#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // RW GPIO Trigger Neg Edge Enable
+#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable
+#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable
+#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status
+#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable
+#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable
#define R_QNC_LPC_PM1BLK 0x48
#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0
@@ -516,15 +533,15 @@ Definitions beginning with "N_" are the bit position
#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0
// Suggested Value for GPE0BLK = 0x10C0
//
-#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status
+#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status
#define S_QNC_GPE0BLK_GPE0S 4
-#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg
+#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // Clear the status reg
#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE
#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO
#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE
#define N_QNC_GPE0BLK_GPE0S_THRM 12
-#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable
+#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable
#define S_QNC_GPE0BLK_GPE0E 4
#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE
#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO
@@ -559,11 +576,11 @@ Definitions beginning with "N_" are the bit position
#define N_QNC_GPE0BLK_SMIS_SLP 2
#define N_QNC_GPE0BLK_SMIS_SWT 1
-#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well
+#define R_QNC_GPE0BLK_PMCW 0x28 // PM Configuration Core Well
#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable
-#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well
-#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad
+#define R_QNC_GPE0BLK_PMSW 0x2C // PM Config Suspend/Resume Well
+#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Init Sctrachpad
#define R_QNC_LPC_ACTL 0x58
#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00
@@ -587,10 +604,10 @@ Definitions beginning with "N_" are the bit position
#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
#define R_QNC_LPC_WDTBA 0x84
-// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN
+// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)-------BEGIN
#define R_QNC_LPC_WDT_WDTCR 0x10
#define R_QNC_LPC_WDT_WDTLR 0x18
-// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END
+// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)---------END
#define R_QNC_LPC_FWH_BIOS_DEC 0xD4
#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)
@@ -619,7 +636,8 @@ Definitions beginning with "N_" are the bit position
//---------------------------------------------------------------------------
// Fixed IO Decode on QuarkNcSocId
//
-// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master
+// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B): R/W 8259 master
+// 30h(2B) 34h(2B) 38h(2B) 3Ch(2B): R/W 8259 master
// 40h(3B): R/W 8254
// 43h(1B): W 8254
// 50h(3B): R/W 8254
@@ -639,8 +657,10 @@ Definitions beginning with "N_" are the bit position
// 84h(3B): R/W Internal/LPC
// 88h(1B): R/W Internal/LPC
// 8Ch(3B): R/W Internal/LPC
-// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave
+// A0h(2B) A4h(2B) A8h(2B) ACh(2B): R/W 8259 slave
+// B0h(2B): R/W 8259 slave
// B2h(1B) B3h(1B): R/W Power management
+// B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave
// 3B0h-3BBh: R/W VGA
// 3C0h-3DFh: R/W VGA
// CF8h(4B): R/W Internal
@@ -677,70 +697,81 @@ Definitions beginning with "N_" are the bit position
#define R_QNC_PCIE_BNUM 0x18
#define R_QNC_PCIE_CAP_PTR 0x34
-#define PCIE_CAPID 0x10 //PCIE Capability ID
-#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID
-#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset
-#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset
-#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset
-#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset
-#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset
-
-#define R_QNC_PCIE_XCAP 0x42 //~ 43h
-#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented
-#define R_QNC_PCIE_DCAP 0x44 //~ 47h
-#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency
-#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency
-#define R_QNC_PCIE_DCTL 0x48 //~ 49h
-#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable
-#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable
-#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable
-#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable
-#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh
-#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported
-#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask
-#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask
-#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask
-#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask
-#define R_QNC_PCIE_LCTL 0x50 //~ 51h
-#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration
-#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link
-#define R_QNC_PCIE_LSTS 0x52 //~ 53h
-#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration
-#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training
-#define R_QNC_PCIE_SLCAP 0x54 //~ 57h
-#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F
-#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7]
-#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7]
-#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19]
-#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
-#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable
-#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable
-#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable
-#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
-#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected
-#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed
-#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed
-#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh
-#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable
-#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable
-#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable
-#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable
-#define R_QNC_PCIE_SVID 0x94 //~ 97h
-#define R_QNC_PCIE_CCFG 0xD0 //~ D3h
-#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable
-#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size
-#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size
-#define R_QNC_PCIE_MPC2 0xD4 //~ D7h
-#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode
-#define R_QNC_PCIE_MPC 0xD8 //~ DBh
-#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable
-#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable
-
-#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable
-#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable
-#define R_QNC_PCIE_IOSFSBCTL 0xF6
-#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter.
-#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE.
+#define PCIE_CAPID 0x10 //PCIE Capability ID
+#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID
+#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability offset
+#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability offset
+#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset
+#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset
+#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability offset
+
+#define R_QNC_PCIE_XCAP 0x42 //~ 43h
+#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented
+#define R_QNC_PCIE_DCAP 0x44 //~ 47h
+// L1 Acceptable exit latency
+#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9)
+// L0 Acceptable exit latency
+#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6)
+#define R_QNC_PCIE_DCTL 0x48 //~ 49h
+// Reporting Enables
+#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request
+#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error
+#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error
+#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error
+#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh
+#define B_QNC_PCIE_LCAP_CPM (BIT18) //clk Pwr Mgmt supported
+// Exit latency mask
+#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 ELM
+#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 ELM
+// Active state link PM support
+#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10)
+#define V_QNC_PCIE_LCAP_APMS_OFFSET 10
+#define R_QNC_PCIE_LCTL 0x50 //~ 51h
+#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock config
+#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link
+#define R_QNC_PCIE_LSTS 0x52 //~ 53h
+#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration
+#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training
+#define R_QNC_PCIE_SLCAP 0x54 //~ 57h
+#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F
+// Slot power limit value [14:7]
+#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value
+#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit offset
+// Slot number is [31:19]
+#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset
+#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
+#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable
+#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable
+#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable
+#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
+#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State
+#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed
+#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attn Button Pressed
+#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh
+// Root PCI-E Interrupt enables
+#define B_QNC_PCIE_RCTL_PIE (BIT3) // PME Interrupt Enable
+#define B_QNC_PCIE_RCTL_SFE (BIT2) // Fatal Error Enable
+#define B_QNC_PCIE_RCTL_SNE (BIT1) // Non-Fatal Error Enable
+#define B_QNC_PCIE_RCTL_SCE (BIT0) // Correctable Error Enbl
+#define R_QNC_PCIE_SVID 0x94 //~ 97h
+#define R_QNC_PCIE_CCFG 0xD0 //~ D3h
+// Upstream
+#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Posted Split Disable
+#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Non-Posted Rqstd Size
+#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Posted Request Size
+#define R_QNC_PCIE_MPC2 0xD4 //~ D7h
+#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Tx Md
+#define R_QNC_PCIE_MPC 0xD8 //~ DBh
+#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable
+#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable
+
+#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable
+#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable
+#define R_QNC_PCIE_IOSFSBCTL 0xF6
+// IOSF Sideband ISM Idle Counter.
+#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0)
+// Never transition to IDLE.
+#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0)
#define V_PCIE_MAX_TRY_TIMES 200
@@ -756,44 +787,52 @@ Definitions beginning with "N_" are the bit position
#define IOAPIC_SIZE 0x1000
//
-// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h)
+// Chipset configuration registers RCBA - "Root Complex Base Address"
+// (D31:F0:RF0h)
// Suggested Value for RCBA = 0xFED1C000
//
-#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB
-#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status
-#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown
-#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status
-#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status
-#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress
-
-#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control
-#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable
-#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64)
-#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer
-#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer
-#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence
-#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go
-
-#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address
-#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask
-#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0
-#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration
-#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration
+#define R_QNC_RCRB_SPIBASE 0x3020 // Serial Peripheral Interface in RCRB
+#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status
+#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown
+#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status
+#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status
+#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress
+
+#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control
+#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable
+#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,
+ // 32,40,48,56,64)
+#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer
+#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer
+#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence
+#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go
+
+#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address
+#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask
+#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08)
+// SPI Data 0
+#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54)
+// Prefix Opcode Configuration
+#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56)
+// Opcode Type Configuration
#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0
#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)
#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)
#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)
-#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU
-
-#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0.
-#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1.
-#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2.
-#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers.
-
-#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route
-#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route
-#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route
-#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route
+// Opcode Menu Configuration //R_OPMENU
+#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58)
+
+// Protected BIOS Range 0 - 2
+#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60)
+#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64)
+#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68)
+// Write Protection Enable for above 3 registers.
+#define B_QNC_RCRB_SPIPBRn_WPE (BIT31)
+
+#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route
+#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route
+#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route
+#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route
#endif
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 1aecf6f..2ddc214 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015-2016 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -60,7 +60,7 @@
#define PCIE_PORT1_DEV PCIE_DEV
#define PCIE_PORT1_FUNC 1
-#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC)
+#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC)
#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC)
/* Platform Controller Unit */
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 8be7f83..1695297 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -226,7 +226,8 @@ enum {
/* Time delays */
#define TIME_DELAY_USEC(value_) \
- SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, MICROSECOND_DELAY)
+ SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, \
+ MICROSECOND_DELAY)
/* USB register access macros */
#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c
index e57b717..aefbaf6 100644
--- a/src/soc/intel/quark/lpc.c
+++ b/src/soc/intel/quark/lpc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,7 +24,7 @@
static void pmc_read_resources(device_t dev)
{
- unsigned index = 0;
+ unsigned int index = 0;
struct resource *res;
/* Get the normal PCI resources of this device. */
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index d58fd1f..5c4629b 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,7 +27,7 @@ static uint16_t get_gpe0_address(uint32_t reg_address)
/* Get the GPE0 base address */
gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK);
- ASSERT (gpe0_base_address >= 0x80000000);
+ ASSERT(gpe0_base_address >= 0x80000000);
gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK;
/* Return the GPE0 register address */
@@ -41,7 +41,7 @@ static uint32_t *get_gpio_address(uint32_t reg_address)
/* Get the GPIO base address */
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1);
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
- ASSERT (gpio_base_address != 0x00000000);
+ ASSERT(gpio_base_address != 0x00000000);
/* Return the GPIO register address */
return (uint32_t *)(gpio_base_address + reg_address);
@@ -54,7 +54,7 @@ void *get_i2c_address(void)
/* Get the GPIO base address */
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0);
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
- ASSERT (gpio_base_address != 0x00000000);
+ ASSERT(gpio_base_address != 0x00000000);
/* Return the GPIO register address */
return (void *)gpio_base_address;
@@ -66,7 +66,7 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address)
/* Get the GPIO base address */
gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE);
- ASSERT (gpio_base_address >= 0x80000000);
+ ASSERT(gpio_base_address >= 0x80000000);
gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
/* Return the GPIO register address */
@@ -144,7 +144,7 @@ void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address)
{
/* Read the CPU CRx register */
- switch(reg_address) {
+ switch (reg_address) {
case 0:
return read_cr0();
@@ -157,7 +157,7 @@ static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address)
static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value)
{
/* Write the CPU CRx register */
- switch(reg_address) {
+ switch (reg_address) {
default:
die("ERROR - Unsupported CPU register!\n");
@@ -419,7 +419,9 @@ static void reg_write(struct reg_script_context *ctx)
case MICROSECOND_DELAY:
/* The actual delay is >= the requested delay */
if (ctx->display_features) {
- /* Higher baud-rates will reduce the impact of displaying this message */
+ /* Higher baud-rates will reduce the impact of
+ * displaying this message
+ */
printk(BIOS_INFO, "Delay %lld uSec\n", step->value);
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
}
@@ -433,7 +435,7 @@ static void reg_write(struct reg_script_context *ctx)
}
}
-msr_t soc_msr_read(unsigned index)
+msr_t soc_msr_read(unsigned int index)
{
uint32_t offset;
union {
@@ -455,7 +457,7 @@ msr_t soc_msr_read(unsigned index)
return value.msr;
}
-void soc_msr_write(unsigned index, msr_t msr)
+void soc_msr_write(unsigned int index, msr_t msr)
{
uint32_t offset;
union {
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 17080a3..4d7f7c9 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -107,9 +107,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
/* Locate the configuration data from devicetree.cb */
dev = dev_find_slot(0, LPC_DEV_FUNC);
- if (!dev) {
+ if (!dev)
die("ERROR - LPC device not found!");
- }
config = dev->chip_info;
/* Update the architectural UPD values. */
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