[coreboot-gerrit] New patch to review for coreboot: AGESA: BIST is already preserved
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Mar 7 16:13:23 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18625
-gerrit
commit 3900a5cc1c10b4643fd0aa8b8541df8acc08b371
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Nov 23 21:29:26 2016 +0200
AGESA: BIST is already preserved
Officialy we enter with BIST in %eax, but %ebp is old backup register.
Note that post_code() destroys %al.
Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/cache_as_ram.inc | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index 6c6f697..c641afa 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -28,7 +28,6 @@
/*
* XMM map:
- * xmm0: BIST
*/
.code32
@@ -36,6 +35,9 @@
cache_as_ram_setup:
+ /* Preserve BIST. */
+ movl %eax, %ebp
+
post_code(0xa0)
/* enable SSE2 128bit instructions */
@@ -45,11 +47,9 @@ cache_as_ram_setup:
orl $(3<<9), %eax
movl %eax, %cr4
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
post_code(0xa1)
+ /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
AMD_ENABLE_STACK
/* Align the stack to 128 bits. No harm on i386, required on x86_64? */
@@ -100,23 +100,22 @@ cache_as_ram_setup:
.code64
- call early_all_cores
+ /* Calling conventions preserve BIST in %ebp. */
- /* Pass the BIST result */
- cvtsd2si %xmm0, %edi
+ call early_all_cores
+ movl %ebp, %edi
call romstage_main
.code32
#else
- call early_all_cores
+ /* Calling conventions preserve BIST in %ebp. */
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
+ call early_all_cores
- pushl %edx /* bist */
+ pushl %ebp
call romstage_main
#endif
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