[coreboot-gerrit] Patch set updated for coreboot: AGESA_LEGACY: Apply final cleanup and file removals
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Mar 7 18:05:20 CET 2017
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18633
-gerrit
commit 3dbacf18a5602df1b8a8ec93ac746e9b77259a6b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat Mar 4 12:59:14 2017 +0200
AGESA_LEGACY: Apply final cleanup and file removals
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/amd/agesa/Kconfig | 11 -
src/cpu/amd/agesa/Makefile.inc | 5 -
src/cpu/amd/agesa/amd_late_init.c | 42 ---
src/cpu/amd/agesa/cache_as_ram_legacy.inc | 172 ----------
src/cpu/amd/agesa/family12/Makefile.inc | 2 +-
src/cpu/amd/agesa/family12/romstage.c | 22 --
src/cpu/amd/agesa/family14/Makefile.inc | 2 +-
src/cpu/amd/agesa/family14/romstage.c | 37 ---
src/cpu/amd/agesa/family15/Makefile.inc | 2 +-
src/cpu/amd/agesa/family15/romstage.c | 27 +-
src/cpu/amd/agesa/family15rl/Makefile.inc | 2 +-
src/cpu/amd/agesa/family15rl/romstage.c | 31 --
src/cpu/amd/agesa/family15tn/Makefile.inc | 2 +-
src/cpu/amd/agesa/family15tn/romstage.c | 30 --
src/cpu/amd/agesa/family16kb/Makefile.inc | 2 +-
src/cpu/amd/agesa/family16kb/romstage.c | 31 --
src/cpu/amd/agesa/romstage.c | 32 +-
src/cpu/amd/agesa/s3_resume.c | 42 ---
src/cpu/amd/agesa/s3_resume.h | 1 -
src/include/cpu/amd/car.h | 2 +-
src/northbridge/amd/agesa/Makefile.inc | 5 -
src/northbridge/amd/agesa/agesawrapper.c | 355 ---------------------
src/northbridge/amd/agesa/agesawrapper.h | 66 ----
src/northbridge/amd/agesa/family12/Makefile.inc | 2 -
src/northbridge/amd/agesa/family12/northbridge.c | 22 --
src/northbridge/amd/agesa/family14/Makefile.inc | 2 -
src/northbridge/amd/agesa/family14/northbridge.c | 31 --
src/northbridge/amd/agesa/family15/northbridge.c | 19 --
src/northbridge/amd/agesa/family15rl/Makefile.inc | 2 -
src/northbridge/amd/agesa/family15rl/northbridge.c | 19 --
src/northbridge/amd/agesa/family15tn/Makefile.inc | 2 -
src/northbridge/amd/agesa/family15tn/northbridge.c | 19 --
src/northbridge/amd/agesa/family16kb/Makefile.inc | 2 -
src/northbridge/amd/agesa/family16kb/northbridge.c | 19 --
src/northbridge/amd/agesa/oem_s3.c | 1 -
src/southbridge/amd/agesa/hudson/Makefile.inc | 2 -
src/southbridge/amd/agesa/hudson/agesawrapper.c | 78 -----
37 files changed, 23 insertions(+), 1120 deletions(-)
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index e43d4b0..ae5e854 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -34,17 +34,6 @@ config CPU_AMD_AGESA
if CPU_AMD_AGESA
-config AGESA_LEGACY
- def_bool n
-
-config AGESA_LEGACY_WRAPPER
- bool
- default AGESA_LEGACY
-
-config AGESA_NO_LEGACY
- bool
- default !AGESA_LEGACY
-
config XIP_ROM_SIZE
hex
default 0x100000
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index b5bb8d9..b9dae57 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -23,16 +23,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
ramstage-y += s3_mtrr.c
-ifeq ($(CONFIG_AGESA_LEGACY), y)
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
-else
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
romstage-y += romstage.c
-endif
romstage-y += heapmanager.c
ramstage-y += heapmanager.c
-ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += amd_late_init.c
ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
deleted file mode 100644
index a55ebd8..0000000
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <bootstate.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#if CONFIG_AMD_SB_CIMX
-#include <sb_cimx.h>
-#endif
-
-static void agesawrapper_post_device(void *unused)
-{
- if (acpi_is_wakeup_s3())
- return;
-
- agesawrapper_amdinitlate();
-
-#if CONFIG_AMD_SB_CIMX
- sb_Late_Post();
-#endif
- if (!acpi_s3_resume_allowed())
- return;
-
- agesawrapper_amdS3Save();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
- agesawrapper_post_device, NULL);
diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
deleted file mode 100644
index d088cc1..0000000
--- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/******************************************************************************
- * AMD Generic Encapsulated Software Architecture
- *
- * $Workfile:: cache_as_ram.inc
- *
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
- *
- ******************************************************************************
- */
-
-#include "gcccar.inc"
-#include <cpu/x86/cache.h>
-
-/*
- * XMM map:
- * xmm0: BIST
- * xmm1: backup ebx -- cpu_init_detected
- */
-
-.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
-
-cache_as_ram_setup:
-
- post_code(0xa0)
-
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3<<9), %eax
- movl %eax, %cr4
-
- /* Get the cpu_init_detected */
- mov $1, %eax
- cpuid
- shr $24, %ebx
-
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
- /* for normal part %ebx already contain cpu_init_detected from fallback call */
-
- /* Save the cpu_init_detected */
- cvtsi2sd %ebx, %xmm1
-
- post_code(0xa1)
-
- AMD_ENABLE_STACK
-
-#ifdef __x86_64__
- /* switch to 64 bit long mode */
- mov %esi, %ecx
- add $0, %ecx # core number
- xor %eax, %eax
- lea (0x1000+0x23)(%ecx), %edi
- mov %edi, (%ecx)
- mov %eax, 4(%ecx)
-
- lea 0x1000(%ecx), %edi
- movl $0x000000e3, 0x00(%edi)
- movl %eax, 0x04(%edi)
- movl $0x400000e3, 0x08(%edi)
- movl %eax, 0x0c(%edi)
- movl $0x800000e3, 0x10(%edi)
- movl %eax, 0x14(%edi)
- movl $0xc00000e3, 0x18(%edi)
- movl %eax, 0x1c(%edi)
-
- # load ROM based identity mapped page tables
- mov %ecx, %eax
- mov %eax, %cr3
-
- # enable PAE
- mov %cr4, %eax
- bts $5, %eax
- mov %eax, %cr4
-
- # enable long mode
- mov $0xC0000080, %ecx
- rdmsr
- bts $8, %eax
- wrmsr
-
- # enable paging
- mov %cr0, %eax
- bts $31, %eax
- mov %eax, %cr0
-
- # use call far to switch to 64-bit code segment
- ljmp $0x18, $1f
-1:
- /* Pass the cpu_init_detected */
- cvtsd2si %xmm1, %esi
-
- /* Pass the BIST result */
- cvtsd2si %xmm0, %edi
-
- /* align the stack */
- and $0xFFFFFFF0, %esp
-
- .code64
- call cache_as_ram_main
-
- call copy_and_run
-
- .code32
-
-#else
-
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
-
- /* Restore the cpu_init_detected */
- cvtsd2si %xmm1, %ebx
-
- pushl %ebx /* init detected */
- pushl %edx /* bist */
- call cache_as_ram_main
-
- call copy_and_run
-
-#endif
-
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
-
-disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
- /* Disable cache */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- AMD_DISABLE_STACK
-
- /* enable cache */
- movl %cr0, %eax
- andl $0x9fffffff, %eax
- movl %eax, %cr0
- xorl %eax, %eax
-
- /* Restore the return stack */
- wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
-
-cache_as_ram_setup_out:
-#ifdef __x86_64__
-.code64
-#endif
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 5673c6b..1a7465d 100644
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -28,7 +28,7 @@
#*****************************************************************************
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
index c616ed7..e803f60 100644
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -13,10 +13,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -37,23 +35,3 @@ void platform_once(struct sysinfo *cb)
board_BeforeAgesa(cb);
}
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x36);
- agesawrapper_amdinitreset();
-
- post_code(0x37);
- agesawrapper_amdinitearly();
-
- post_code(0x38);
- agesawrapper_amdinitpost();
-
- post_code(0x39);
- printk(BIOS_DEBUG, "sb_before_pci_init ");
- sb_before_pci_init();
- printk(BIOS_DEBUG, "passed.\n");
-
- post_code(0x40);
- agesawrapper_amdinitenv();
-}
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 71d15fb..3da8dd5 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -14,7 +14,7 @@
#
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
index 6bbd496..67affbf 100644
--- a/src/cpu/amd/agesa/family14/romstage.c
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -13,10 +13,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -33,38 +31,3 @@ void platform_once(struct sysinfo *cb)
board_BeforeAgesa(cb);
}
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- if (!cb->s3resume) {
- printk(BIOS_INFO, "Normal boot\n");
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
-
- post_code(0x42);
- amd_initenv();
-
- } else {
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
-
- agesawrapper_amdinitresume();
-
- post_code(0x61);
-
- agesawrapper_amds3laterestore();
-
- post_code(0x62);
- }
-}
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
index d7cdff7..d01cb2a 100644
--- a/src/cpu/amd/agesa/family15/Makefile.inc
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -22,7 +22,7 @@ subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index b07550c..276071e 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -19,9 +19,8 @@
#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
@@ -47,18 +46,10 @@ void platform_once(struct sysinfo *cb)
board_BeforeAgesa(cb);
}
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x3B);
- agesawrapper_amdinitearly();
-
- post_code(0x3C);
-
+#if 0
+ /* after AMD_INIT_EARLY, before AMD_INIT_POST */
nb_Ht_Init();
- post_code(0x3D);
+
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
@@ -66,12 +57,4 @@ void agesa_main(struct sysinfo *cb)
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
-
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- post_code(0x42);
-
-}
+#endif
diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc
index 4fcaff7..d4695b0 100644
--- a/src/cpu/amd/agesa/family15rl/Makefile.inc
+++ b/src/cpu/amd/agesa/family15rl/Makefile.inc
@@ -14,7 +14,7 @@
#
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c
index a9b7bb5..d7c7c11 100644
--- a/src/cpu/amd/agesa/family15rl/romstage.c
+++ b/src/cpu/amd/agesa/family15rl/romstage.c
@@ -13,10 +13,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -29,32 +27,3 @@ void platform_once(struct sysinfo *cb)
{
board_BeforeAgesa(cb);
}
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- if (!cb->s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- } else {
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- }
-
-}
-
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 4fcaff7..d4695b0 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -14,7 +14,7 @@
#
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
index 8766e21..2cf436d 100644
--- a/src/cpu/amd/agesa/family15tn/romstage.c
+++ b/src/cpu/amd/agesa/family15tn/romstage.c
@@ -1,4 +1,3 @@
-
/*
* This file is part of the coreboot project.
*
@@ -14,10 +13,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -31,30 +28,3 @@ void platform_once(struct sysinfo *cb)
{
board_BeforeAgesa(cb);
}
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- if (!cb->s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
- } else {
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- }
-}
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
index 31c3ecf..5c2ba8f 100644
--- a/src/cpu/amd/agesa/family16kb/Makefile.inc
+++ b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -14,7 +14,7 @@
#
romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
index 8409556..d7c7c11 100644
--- a/src/cpu/amd/agesa/family16kb/romstage.c
+++ b/src/cpu/amd/agesa/family16kb/romstage.c
@@ -13,10 +13,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -29,32 +27,3 @@ void platform_once(struct sysinfo *cb)
{
board_BeforeAgesa(cb);
}
-
-void agesa_main(struct sysinfo *cb)
-{
- post_code(0x37);
- agesawrapper_amdinitreset();
-
- post_code(0x39);
- agesawrapper_amdinitearly();
-
- if (!cb->s3resume) {
- post_code(0x40);
- agesawrapper_amdinitpost();
-
- post_code(0x41);
- agesawrapper_amdinitenv();
-
- } else {
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- agesawrapper_amdinitresume();
-
- amd_initcpuio();
- agesawrapper_amds3laterestore();
-
- post_code(0x61);
- }
-}
-
diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c
index 802d8ae..1c5ef12 100644
--- a/src/cpu/amd/agesa/romstage.c
+++ b/src/cpu/amd/agesa/romstage.c
@@ -31,8 +31,7 @@ static void fill_sysinfo(struct sysinfo *cb)
memset(cb, 0, sizeof(*cb));
cb->s3resume = acpi_is_wakeup_s3();
- if (!IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER))
- agesa_set_interface(cb);
+ agesa_set_interface(cb);
}
void * asmlinkage romstage_main(unsigned long bist)
@@ -57,21 +56,14 @@ void * asmlinkage romstage_main(unsigned long bist)
post_code(0x34);
report_bist_failure(bist);
- if (!IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)) {
- agesa_execute_state(cb, AMD_INIT_RESET);
+ agesa_execute_state(cb, AMD_INIT_RESET);
- agesa_execute_state(cb, AMD_INIT_EARLY);
+ agesa_execute_state(cb, AMD_INIT_EARLY);
- if (!cb->s3resume)
- agesa_execute_state(cb, AMD_INIT_POST);
- else
- agesa_execute_state(cb, AMD_INIT_RESUME);
-
- } else {
-
- agesa_main(cb);
-
- }
+ if (!cb->s3resume)
+ agesa_execute_state(cb, AMD_INIT_POST);
+ else
+ agesa_execute_state(cb, AMD_INIT_RESUME);
uintptr_t stack_top = CACHE_TMP_RAMTOP;
if (cb->s3resume) {
@@ -97,12 +89,10 @@ void asmlinkage romstage_after_car(void)
fill_sysinfo(cb);
- if (!IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)) {
- if (!cb->s3resume)
- agesa_execute_state(cb, AMD_INIT_ENV);
- else
- agesa_execute_state(cb, AMD_S3LATE_RESTORE);
- }
+ if (!cb->s3resume)
+ agesa_execute_state(cb, AMD_INIT_ENV);
+ else
+ agesa_execute_state(cb, AMD_S3LATE_RESTORE);
if (cb->s3resume)
set_resume_cache();
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 8aaa25b..34717b9 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -27,30 +27,6 @@
#include "s3_resume.h"
#include <northbridge/amd/agesa/agesa_helper.h>
-static void move_stack_high_mem(void)
-{
- uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
- ROMSTAGE_STACK_CBMEM);
- if (!high_stack)
- halt();
-
- /* TODO: Make the switch with empty stack instead. */
- memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
-
- /* TODO: We only switch stack on BSP. */
-#ifdef __x86_64__
- __asm__
- volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g"
- (high_stack - BSP_STACK_BASE_ADDR)
- :);
-#else
- __asm__
- volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
- (high_stack - BSP_STACK_BASE_ADDR)
- :);
-#endif
-}
-
void set_resume_cache(void)
{
msr_t msr;
@@ -75,21 +51,3 @@ void set_resume_cache(void)
enable_cache();
}
-
-void prepare_for_resume(void)
-{
- if (cbmem_recovery(1)) {
- printk(BIOS_EMERG, "Unable to recover CBMEM\n");
- halt();
- }
-
- post_code(0x62);
- printk(BIOS_DEBUG, "Move CAR stack.\n");
- move_stack_high_mem();
-
- post_code(0x63);
- disable_cache_as_ram();
- printk(BIOS_DEBUG, "CAR disabled.\n");
- set_resume_cache();
-
-}
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index bb65af3..37ce0d5 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -17,7 +17,6 @@
#define S3_RESUME_H
void restore_mtrr(void);
-void prepare_for_resume(void);
void set_resume_cache(void);
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index df03513..e902c52 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -12,7 +12,7 @@ void post_cache_as_ram(void);
void cache_as_ram_switch_stack(void *stacktop);
void cache_as_ram_new_stack(void);
-#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI
+#if IS_ENABLED(CONFIG_CPU_AMD_PI)
void disable_cache_as_ram(void);
#endif
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 992ac55..1d153ac 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -26,13 +26,8 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += def_callouts.c eventlog.c
ramstage-y += def_callouts.c eventlog.c
-ifeq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
-romstage-y += agesawrapper.c
-ramstage-y += agesawrapper.c
-else
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
romstage-y += oem_s3.c
ramstage-y += oem_s3.c
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
deleted file mode 100644
index 61c6bf8..0000000
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
-#include "heapManager.h"
-
-static const struct OEM_HOOK *OemHook = &OemCustomize;
-
-#if defined(__PRE_RAM__)
-
-AGESA_STATUS agesawrapper_amdinitreset(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_RESET_PARAMS AmdResetParams;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
- memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
- AmdParamStruct.AllocationMethod = ByHost;
- AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
- AmdParamStruct.NewStructPtr = &AmdResetParams;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
- AmdResetParams.HtConfig.Depth = 0;
-
- status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitearly(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitEarly)
- OemHook->InitEarly(AmdEarlyParamsPtr);
-
- status = AmdInitEarly(AmdEarlyParamsPtr);
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitpost(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_POST_PARAMS *PostParams;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitPost)
- OemHook->InitPost(PostParams);
-
- status = AmdInitPost(PostParams);
- AGESA_EVENTLOG(status, &PostParams->StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
-
- /* Initialize heap space */
- EmptyHeap();
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitresume(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_RESUME_PARAMS *AmdResumeParamsPtr;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
- AmdParamStruct.AllocationMethod = PreMemHeap;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
-
- AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
-
- AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
- AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- OemInitResume(AmdResumeParamsPtr);
-
- status = AmdInitResume(AmdResumeParamsPtr);
-
- AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitenv(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_ENV_PARAMS *EnvParam;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
- AmdCreateStruct(&AmdParamStruct);
- EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
-
- status = AmdInitEnv(EnvParam);
- AGESA_EVENTLOG(status, &EnvParam->StdHeader);
-
- AmdReleaseStruct(&AmdParamStruct);
- return status;
-}
-
-AGESA_STATUS agesawrapper_amds3laterestore(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdInterfaceParams;
- AMD_S3LATE_PARAMS AmdS3LateParams;
- AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
-
- memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
-
- AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
- AmdInterfaceParams.AllocationMethod = ByHost;
- AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
- AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
- AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdS3LateParamsPtr = &AmdS3LateParams;
- AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
-
- AmdCreateStruct(&AmdInterfaceParams);
-
-#if 0
- /* TODO: What to do with NvStorage here? */
- AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0;
-#endif
- AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- OemS3LateRestore(AmdS3LateParamsPtr);
-
- status = AmdS3LateRestore(AmdS3LateParamsPtr);
- AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- return status;
-}
-
-#else /* __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amdinitmid(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
- AMD_MID_PARAMS *MidParam;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
- AmdCreateStruct(&AmdParamStruct);
-
- /* OEM Should Customize the defaults through this hook. */
- MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr;
- if (OemHook->InitMid)
- OemHook->InitMid(MidParam);
-
- status = AmdInitMid(MidParam);
- AGESA_EVENTLOG(status, &MidParam->StdHeader);
- AmdReleaseStruct(&AmdParamStruct);
-
- return status;
-}
-
-AGESA_STATUS agesawrapper_amdS3Save(void)
-{
- AGESA_STATUS status;
- AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
- AMD_INTERFACE_PARAMS AmdInterfaceParams;
-
- memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
- AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdInterfaceParams.AllocationMethod = PostMemDram;
- AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
- AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
- AmdInterfaceParams.StdHeader.Func = 0;
- AmdCreateStruct(&AmdInterfaceParams);
-
- AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
- AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
-
- status = AmdS3Save(AmdS3SaveParamsPtr);
- AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- OemS3Save(AmdS3SaveParamsPtr);
-
- AmdReleaseStruct(&AmdInterfaceParams);
-
- return status;
-}
-
-/* We will reference AmdLateParams later to copy ACPI tables. */
-static AMD_LATE_PARAMS *AmdLateParams = NULL;
-
-AGESA_STATUS agesawrapper_amdinitlate(void)
-{
- AGESA_STATUS status;
- AMD_INTERFACE_PARAMS AmdParamStruct;
-
- memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
- AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
- AmdParamStruct.AllocationMethod = PostMemDram;
- AmdParamStruct.StdHeader.AltImageBasePtr = 0;
- AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
- AmdParamStruct.StdHeader.Func = 0;
- AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \
- IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
- AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-#endif
-
- AmdCreateStruct(&AmdParamStruct);
- AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
- status = AmdInitLate(AmdLateParams);
- AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */
- return status;
-}
-
-void *agesawrapper_getlateinitptr(int pick)
-{
- ASSERT(AmdLateParams != NULL);
-
- switch (pick) {
- case PICK_DMI:
- return AmdLateParams->DmiTable;
- case PICK_PSTATE:
- return AmdLateParams->AcpiPState;
- case PICK_SRAT:
- return AmdLateParams->AcpiSrat;
- case PICK_SLIT:
- return AmdLateParams->AcpiSlit;
- case PICK_WHEA_MCE:
- return AmdLateParams->AcpiWheaMce;
- case PICK_WHEA_CMC:
- return AmdLateParams->AcpiWheaCmc;
- case PICK_ALIB:
- return AmdLateParams->AcpiAlib;
- case PICK_IVRS:
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14)
- return NULL;
-#else
- return AmdLateParams->AcpiIvrs;
-#endif
- default:
- return NULL;
- }
- return NULL;
-}
-
-#endif /* __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
-{
- AGESA_STATUS status;
- AP_EXE_PARAMS ApExeParams;
-
- memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS));
-
- ApExeParams.StdHeader.AltImageBasePtr = 0;
- ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout;
- ApExeParams.StdHeader.Func = 0;
- ApExeParams.StdHeader.ImageBasePtr = 0;
- ApExeParams.FunctionNumber = Func;
- ApExeParams.RelatedDataBlock = ConfigPtr;
-
- status = AmdLateRunApTask(&ApExeParams);
- AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
- ASSERT(status == AGESA_SUCCESS);
-
- return status;
-}
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
deleted file mode 100644
index 40b5f22..0000000
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AGESAWRAPPER_H_
-#define _AGESAWRAPPER_H_
-
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-
-#include <stdint.h>
-#include "Porting.h"
-#include "AGESA.h"
-
-AGESA_STATUS agesawrapper_amdinitreset(void);
-AGESA_STATUS agesawrapper_amdinitearly(void);
-AGESA_STATUS agesawrapper_amdinitenv(void);
-AGESA_STATUS agesawrapper_amdinitlate(void);
-AGESA_STATUS agesawrapper_amdinitpost(void);
-AGESA_STATUS agesawrapper_amdinitmid(void);
-
-AGESA_STATUS agesawrapper_amdinitresume(void);
-AGESA_STATUS agesawrapper_amdS3Save(void);
-AGESA_STATUS agesawrapper_amds3laterestore(void);
-
-AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
-AGESA_STATUS agesawrapper_fchs3laterestore(void);
-
-#define AGESA_EVENTLOG(status, stdheader) \
- agesawrapper_trace(status, stdheader, __func__)
-
-struct OEM_HOOK
-{
- /* romstage */
- AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *);
- AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *);
-
- /* ramstage */
- AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *);
-};
-
-extern const struct OEM_HOOK OemCustomize;
-
-#else
-
-/* Defined to make unused agesa_main() build. */
-static inline int agesawrapper_amdinitreset(void) { return -1; }
-static inline int agesawrapper_amdinitearly(void) { return -1; }
-static inline int agesawrapper_amdinitenv(void) { return -1; }
-static inline int agesawrapper_amdinitpost(void) { return -1; }
-static inline int agesawrapper_amdinitresume(void) { return -1; }
-static inline int agesawrapper_amds3laterestore(void) { return -1; }
-
-#endif /* IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) */
-
-#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc
index 41c40c3..ad39325 100644
--- a/src/northbridge/amd/agesa/family12/Makefile.inc
+++ b/src/northbridge/amd/agesa/family12/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index d272d7f..7dba9a5 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -33,7 +33,6 @@
#include "sb_cimx.h"
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -635,26 +634,6 @@ static void domain_set_resources(device_t dev)
}
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
- /* Must be called after PCI enumeration and resource allocation */
-#if CONFIG_AMD_SB_CIMX
- sb_After_Pci_Init();
- sb_Mid_Post_Init();
-#endif
-
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-#endif
-}
-
-
/* Bus related code */
static void cpu_bus_init(device_t dev)
@@ -795,7 +774,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
};
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 41c40c3..ad39325 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 872d14c..2f04a01 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -31,13 +31,10 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h>
-#endif
#define FX_DEVS 1
@@ -617,33 +614,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
}
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- /* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
-
-#if CONFIG_AMD_SB_CIMX
- if (!acpi_is_wakeup_s3()) {
- sb_After_Pci_Init();
- sb_Mid_Post_Init();
- } else {
- sb_After_Pci_Restore_Init();
- }
-#endif
-
-
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
-
- printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
-#endif
-}
-
static const char *domain_acpi_name(struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -824,7 +794,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.acpi_name = domain_acpi_name,
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 44c1b82..f1e6a99 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -38,7 +38,6 @@
#include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include "sb_cimx.h"
@@ -635,23 +634,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- /* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
-
-#if CONFIG_AMD_SB_CIMX
- sb_After_Pci_Init();
-#endif
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__);
-#endif
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -854,7 +836,6 @@ static void f15_pci_domain_scan_bus(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = f15_pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc
index d6cbc1f..9e9283c 100644
--- a/src/northbridge/amd/agesa/family15rl/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc
@@ -18,7 +18,5 @@ romstage-y += dimmSpd.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index 255e7d2..f0b9c38 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -39,7 +39,6 @@
#include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -632,23 +631,6 @@ static void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(struct device *dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
-#endif
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -847,7 +829,6 @@ static void domain_set_resources(struct device *dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc
index d6cbc1f..9e9283c 100644
--- a/src/northbridge/amd/agesa/family15tn/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc
@@ -18,7 +18,5 @@ romstage-y += dimmSpd.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 6eaaa61..e5a540c 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -38,7 +38,6 @@
#include <cpu/amd/amdfam15.h>
#include <cpuRegisters.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -631,23 +630,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
-#endif
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -844,7 +826,6 @@ static void domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc
index 25e3cc8..3021ef4 100644
--- a/src/northbridge/amd/agesa/family16kb/Makefile.inc
+++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index e7b07e8..8517e9a 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -38,7 +38,6 @@
#include <cpu/amd/amdfam16.h>
#include <cpuRegisters.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -646,23 +645,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3laterestore();
-
- /* Must be called after PCI enumeration and resource allocation */
- if (!acpi_is_wakeup_s3()) {
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio();
-
- agesawrapper_amdinitmid();
- }
- printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
-#endif
-}
-
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -863,7 +845,6 @@ static void domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
- .enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index b149c10..5f1cc9e 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -19,7 +19,6 @@
#include <cbmem.h>
#include <program_loading.h>
#include <cpu/amd/agesa/s3_resume.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <AGESA.h>
#include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index b1c56cb..527c9be 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -10,8 +10,6 @@ ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sd.c
-ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += agesawrapper.c
-
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c
deleted file mode 100644
index 2a8581e..0000000
--- a/src/southbridge/amd/agesa/hudson/agesawrapper.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <cpu/x86/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "cpuRegisters.h"
-#include "cpuCacheInit.h"
-#include "cpuApicUtilities.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "Dispatcher.h"
-#include "cpuCacheInit.h"
-#include "amdlib.h"
-#include "Filecode.h"
-#include "heapManager.h"
-#include "FchPlatform.h"
-#include "Fch.h"
-#include <arch/io.h>
-#include <device/device.h>
-#include "hudson.h"
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-//#error Use of GetHeapBase() is incorrect or at least suspicious
-#endif
-
-AGESA_STATUS agesawrapper_fchs3earlyrestore (void)
-{
- FCH_DATA_BLOCK FchParams;
- AMD_CONFIG_PARAMS StdHeader;
-
- StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10;
- StdHeader.AltImageBasePtr = 0;
- StdHeader.CalloutPtr = &GetBiosCallout;
- StdHeader.Func = 0;
- StdHeader.ImageBasePtr = 0;
-
- FchParams.StdHeader = &StdHeader;
- s3_resume_init_data(&FchParams);
- FchInitS3EarlyRestore(&FchParams);
-
- return AGESA_SUCCESS;
-}
-
-AGESA_STATUS agesawrapper_fchs3laterestore (void)
-{
- FCH_DATA_BLOCK FchParams;
- AMD_CONFIG_PARAMS StdHeader;
-
- StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10;
- StdHeader.AltImageBasePtr = 0;
- StdHeader.CalloutPtr = &GetBiosCallout;
- StdHeader.Func = 0;
- StdHeader.ImageBasePtr = 0;
-
- FchParams.StdHeader = &StdHeader;
- s3_resume_init_data(&FchParams);
- FchInitS3LateRestore(&FchParams);
-
- return AGESA_SUCCESS;
-}
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