[coreboot-gerrit] New patch to review for coreboot: drivers/intel/fsp2_0: Use tabs for indent
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Fri Mar 10 17:54:14 CET 2017
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18742
-gerrit
commit 06a7e6ebac48ed6cf2221bc956e3a15c65cd0c9f
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Fri Mar 10 08:25:46 2017 -0800
drivers/intel/fsp2_0: Use tabs for indent
Fix the following warning detected by checkpatch.pl:
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp2_0/include/fsp/upd.h | 86 +++++++++++++++---------------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 004d91b..651170f 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -13,52 +13,52 @@
#define _FSP2_0_UPD_H_
struct FSP_UPD_HEADER {
- ///
- /// UPD Region Signature. This signature will be
- /// "XXXXXX_T" for FSP-T
- /// "XXXXXX_M" for FSP-M
- /// "XXXXXX_S" for FSP-S
- /// Where XXXXXX is an unique signature
- ///
- uint64_t Signature;
- ///
- /// Revision of the Data structure. For FSP v2.0 value is 1.
- ///
- uint8_t Revision;
- uint8_t Reserved[23];
+ ///
+ /// UPD Region Signature. This signature will be
+ /// "XXXXXX_T" for FSP-T
+ /// "XXXXXX_M" for FSP-M
+ /// "XXXXXX_S" for FSP-S
+ /// Where XXXXXX is an unique signature
+ ///
+ uint64_t Signature;
+ ///
+ /// Revision of the Data structure. For FSP v2.0 value is 1.
+ ///
+ uint8_t Revision;
+ uint8_t Reserved[23];
} __attribute__((packed));
struct FSPM_ARCH_UPD {
- ///
- /// Revision of the structure. For FSP v2.0 value is 1.
- ///
- uint8_t Revision;
- uint8_t Reserved[3];
- ///
- /// Pointer to the non-volatile storage (NVS) data buffer.
- /// If it is NULL it indicates the NVS data is not available.
- ///
- void *NvsBufferPtr;
- ///
- /// Pointer to the temporary stack base address to be
- /// consumed inside FspMemoryInit() API.
- ///
- void *StackBase;
- ///
- /// Temporary stack size to be consumed inside
- /// FspMemoryInit() API.
- ///
- uint32_t StackSize;
- ///
- /// Size of memory to be reserved by FSP below "top
- /// of low usable memory" for bootloader usage.
- ///
- uint32_t BootLoaderTolumSize;
- ///
- /// Current boot mode.
- ///
- uint32_t BootMode;
- uint8_t Reserved1[8];
+ ///
+ /// Revision of the structure. For FSP v2.0 value is 1.
+ ///
+ uint8_t Revision;
+ uint8_t Reserved[3];
+ ///
+ /// Pointer to the non-volatile storage (NVS) data buffer.
+ /// If it is NULL it indicates the NVS data is not available.
+ ///
+ void *NvsBufferPtr;
+ ///
+ /// Pointer to the temporary stack base address to be
+ /// consumed inside FspMemoryInit() API.
+ ///
+ void *StackBase;
+ ///
+ /// Temporary stack size to be consumed inside
+ /// FspMemoryInit() API.
+ ///
+ uint32_t StackSize;
+ ///
+ /// Size of memory to be reserved by FSP below "top
+ /// of low usable memory" for bootloader usage.
+ ///
+ uint32_t BootLoaderTolumSize;
+ ///
+ /// Current boot mode.
+ ///
+ uint32_t BootMode;
+ uint8_t Reserved1[8];
} __attribute__((packed));
#endif /* _FSP2_0_UPD_H_ */
More information about the coreboot-gerrit
mailing list