[coreboot-gerrit] Patch set updated for coreboot: vendorcode/amd/pi/00670F00: Clarify CAR disable
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Sun Mar 12 01:30:43 CET 2017
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18492
-gerrit
commit c4496de96e77eb1e2759eccb9d3d7667519eb554
Author: Marc Jones <marcj303 at gmail.com>
Date: Fri Feb 24 16:40:41 2017 -0700
vendorcode/amd/pi/00670F00: Clarify CAR disable
Clean up the AMD_DISABLE_STACK_FAMILY_HOOK_F15 to be clear that
it does a wbinvd to preserve the coreboot stack and CAR globals.
The Stoney Ridge uses a different S3 architecture, so this is not
an issue of reserving or relocating the stack on a resume. Remove
the Gardenia cache_disable TODO comment as this clarifies how it
works for Stoney.
Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328
Signed-off-by: Marc Jones <marcj303 at gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
src/mainboard/amd/gardenia/romstage.c | 2 +-
src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 20 +++++++++++++++-----
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 0136a98..9553b03 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER(amdinitpost);
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
+
disable_cache_as_ram();
if (acpi_is_wakeup_s4()) {
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index d6782a3..4005057 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -401,6 +401,14 @@ fam15_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
+* Note: Customized for coreboot:
+* A wbinvd is used to send cache to memory to preserve stack and
+* coreboot CAR globals. This should NOT be used with S3 resume IF the
+* stack/cache area is not reserved and over system memory.
+*
+* This CPU resume path doesn't use CAR, but be careful if porting to
+* other CPUs.
+*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@@ -634,11 +642,13 @@ fam15_disable_stack_remote_read_exit:
# Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
#--------------------------------------------------------------------------
- mov $HWCR, %ecx # MSR:C001_0015h
- _RDMSR
- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
- _WRMSR
- wbinvd #bao # Clear the cache tag RAMs
+ #--------------------------------------------------------------------------
+ # Send cache to memory. Preserve stack and coreboot CAR globals.
+ # This shouldn't be used with S3 resume IF the stack/cache area is
+ # not reserved and over system memory.
+ #--------------------------------------------------------------------------
+ wbinvd # Clear the cache tag RAMs
+
# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
# cmp $01, %bh
# jz 4f
More information about the coreboot-gerrit
mailing list