[coreboot-gerrit] Patch set updated for coreboot: mainboard/amd/gardenia: Remove S4 resume check
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Sun Mar 12 22:00:16 CET 2017
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18494
-gerrit
commit 4847c40822270c3ca4264a66eb455c2ae5c0e030
Author: Marc Jones <marcj303 at gmail.com>
Date: Thu Feb 23 22:06:01 2017 -0700
mainboard/amd/gardenia: Remove S4 resume check
S5 and S4 hardware init path should be identical. If this
hudson register had to be setup for S4 resume, it should also
be set on a normal boot.
Note: These registers are not in public docs, so we also assume
that the values are correct.
Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
src/mainboard/amd/gardenia/romstage.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 9cda7af..2e935cb 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -40,10 +40,8 @@ void cache_as_ram_stage_main(void)
disable_cache_as_ram();
- if (acpi_is_wakeup_s4()) {
- outb(0xEE, PM_INDEX);
- outb(0x8, PM_DATA);
- }
+ outb(0xEE, PM_INDEX);
+ outb(0x8, PM_DATA);
post_code(0x50);
copy_and_run();
More information about the coreboot-gerrit
mailing list