[coreboot-gerrit] Patch set updated for coreboot: intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Wed Mar 15 06:01:25 CET 2017
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18565
-gerrit
commit 5b0e4a3979c7159f5db35cb181ecb3dd13bc5f8c
Author: Subrata Banik <subrata.banik at intel.com>
Date: Sat Mar 4 23:32:41 2017 +0530
intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers
Move all common registers and specific to SOC registers into
a common location to avoid duplication.
Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
.../common/block/include/intelblocks/systemagent.h | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
new file mode 100644
index 0000000..3a72982
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SA_H
+#define SOC_INTEL_COMMON_BLOCK_SA_H
+
+#include <intelblocks/pci_devs.h>
+
+/* System Agent Devices */
+#define SA_DEV_SLOT_ROOT 0x00
+#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
+#define SA_DEV_ROOT _SA_DEV(ROOT)
+
+/* Device 0:0.0 PCI configuration space */
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define GGC 0x50
+
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+
+#endif /* SOC_INTEL_COMMON_BLOCK_SA_H */
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