[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Use common car teardown common code
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Wed Mar 15 13:03:30 CET 2017
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18826
-gerrit
commit abdad4a42108675b15a757dc5e9aa7a7780fad05
Author: Subrata Banik <subrata.banik at intel.com>
Date: Wed Mar 15 17:28:38 2017 +0530
soc/intel/skylake: Use common car teardown common code
Change-Id: I4f8b3360078612f53db63f2bd9021fe34137cd9c
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/drivers/intel/fsp1_1/after_raminit.S | 4 ++--
src/soc/intel/skylake/romstage/car_stage_fsp20.S | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index 3a4116a..cd56ea8 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -32,8 +32,8 @@
#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
- /* SOC specific NEM */
- #include <soc/car_teardown.S>
+ /* chipset_teardown_car() is expected to disable cache-as-ram. */
+ call chipset_teardown_car
#else
.extern fih_car
diff --git a/src/soc/intel/skylake/romstage/car_stage_fsp20.S b/src/soc/intel/skylake/romstage/car_stage_fsp20.S
index c6401fa..5ef8bd6 100644
--- a/src/soc/intel/skylake/romstage/car_stage_fsp20.S
+++ b/src/soc/intel/skylake/romstage/car_stage_fsp20.S
@@ -37,7 +37,8 @@ car_stage_entry:
/* Switch to the stack in RAM */
movl %eax, %esp
- #include <soc/car_teardown.S>
+ /* chipset_teardown_car() is expected to disable cache-as-ram. */
+ call chipset_teardown_car
/* Display the MTRRs */
call soc_display_mtrrs
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