[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Fix spacing issues detected by checkpatch
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 02:35:51 CET 2017
Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/18869 )
Change subject: soc/intel/braswell: Fix spacing issues detected by checkpatch
......................................................................
soc/intel/braswell: Fix spacing issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxE)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no spaces at the start of a line
TEST=Build for cyan
Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
Reviewed-on: https://review.coreboot.org/18869
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Tested-by: build bot (Jenkins)
---
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/chip.h
M src/soc/intel/braswell/gpio.c
M src/soc/intel/braswell/gpio_support.c
M src/soc/intel/braswell/include/soc/gpio.h
5 files changed, 14 insertions(+), 14 deletions(-)
Approvals:
Duncan Laurie: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 0e866a5..163d7a9 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -498,7 +498,7 @@
if (ssdt2->length) {
current += ssdt2->length;
acpi_add_table(rsdp, ssdt2);
- printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2,
+ printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2,
ssdt2->length);
current = acpi_align_current(current);
} else {
@@ -517,7 +517,7 @@
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs)
memset(gnvs, 0, sizeof(*gnvs));
}
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 864f214..fc57a6a 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -34,8 +34,8 @@
#define MEM_LPDDR3 1
enum lpe_clk_src {
- LPE_CLK_SRC_XTAL,
- LPE_CLK_SRC_PLL,
+ LPE_CLK_SRC_XTAL,
+ LPE_CLK_SRC_PLL,
};
enum usb_comp_bg_value {
@@ -74,10 +74,10 @@
int pcie_wake_enable;
/* Program USB2_COMPBG register.
- * [10:7] - select vref to AFE port
- * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
- * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
- */
+ * [10:7] - select vref to AFE port
+ * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
+ * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
+ */
enum usb_comp_bg_value usb_comp_bg;
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
index b85cde3..a742f73 100644
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -59,9 +59,9 @@
/* GPIO Community descriptions */
static const struct gpio_bank gpnorth_community = {
.gpio_count = GP_NORTH_COUNT,
- .gpio_to_pad = gpncommunity_gpio_to_pad ,
- .pad_base = COMMUNITY_GPNORTH_BASE ,
- .has_gpe_en = GPE_CAPABLE ,
+ .gpio_to_pad = gpncommunity_gpio_to_pad,
+ .pad_base = COMMUNITY_GPNORTH_BASE,
+ .has_gpe_en = GPE_CAPABLE,
.has_wake_en = 1,
};
diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c
index 73f829b..5ca34ec 100644
--- a/src/soc/intel/braswell/gpio_support.c
+++ b/src/soc/intel/braswell/gpio_support.c
@@ -103,7 +103,7 @@
static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg)
{
int comm = 0;
- int pad_num =0;
+ int pad_num = 0;
uint32_t *pad_config0_reg;
uint32_t *pad_config1_reg;
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
@@ -143,7 +143,7 @@
int gpio_get(gpio_t gpio_num)
{
int comm = 0;
- int pad_num =0;
+ int pad_num = 0;
uint32_t *pad_config0_reg;
u32 pad_value;
int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 3c56f6a..4abc9f4 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -315,7 +315,7 @@
| PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
| PAD_INT_SEL(int_sel), \
.pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
- .int_mask = 1 ,\
+ .int_mask = 1,\
.wake_mask = 1 }
#define GPIO_SMI(int_sel) \
--
To view, visit https://review.coreboot.org/18869
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Gerrit-MessageType: merged
Gerrit-Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins)
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