[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Add int to unsigned
Lee Leahy (Code Review)
gerrit at coreboot.org
Fri Mar 17 03:11:01 CET 2017
Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/18873 )
Change subject: soc/intel/broadwell: Add int to unsigned
......................................................................
soc/intel/broadwell: Add int to unsigned
Fix the following issue detected by checkpatch:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=None
Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
M src/soc/intel/broadwell/bootblock/cpu.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/gpio.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/gpio.h
M src/soc/intel/broadwell/include/soc/romstage.h
M src/soc/intel/broadwell/include/soc/smbus.h
M src/soc/intel/broadwell/iobp.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/smbus.c
M src/soc/intel/broadwell/smbus_common.c
M src/soc/intel/broadwell/spi.c
15 files changed, 42 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/18873/1
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index 0f665bd..133b1a4 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -24,9 +24,8 @@
#include <soc/rcba.h>
#include <soc/msr.h>
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
-
+static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+ unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index aa82a9d..8176c8e 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -61,7 +61,8 @@
.init = &broadwell_init_pre_device,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
if (!vendor || !device)
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index cc26c75..2675aa5 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -323,8 +323,8 @@
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
- unsigned power_unit;
- unsigned tdp, min_power, max_power, max_time;
+ unsigned int power_unit;
+ unsigned int tdp, min_power, max_power, max_time;
u8 power_limit_1_val;
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index fe223f7..e00fa25 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -24,7 +24,8 @@
#include <soc/ehci.h>
#include <soc/pch.h>
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;
diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c
index 3cbc60d..50f6a29 100644
--- a/src/soc/intel/broadwell/gpio.c
+++ b/src/soc/intel/broadwell/gpio.c
@@ -161,11 +161,11 @@
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
+ unsigned int bitmask = 1;
+ unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 6459f90..fc04401 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -277,7 +277,7 @@
static int gtt_poll(u32 reg, u32 mask, u32 value)
{
- unsigned try = GT_RETRY;
+ unsigned int try = GT_RETRY;
u32 data;
while (try--) {
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
index ff51283..7aba8dc 100644
--- a/src/soc/intel/broadwell/include/soc/gpio.h
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -186,6 +186,6 @@
* Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
#endif
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index e28d9b3..ec733f8 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -48,7 +48,7 @@
void intel_early_me_status(void);
void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_spi_read_wpsr(u8 *sr);
diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h
index 0a7dbae..4d9d3e1 100644
--- a/src/soc/intel/broadwell/include/soc/smbus.h
+++ b/src/soc/intel/broadwell/include/soc/smbus.h
@@ -40,9 +40,9 @@
#define SMBUS_TIMEOUT (10 * 1000 * 100)
#define SMBUS_SLAVE_ADDR 0x24
-int do_smbus_read_byte(unsigned smbus_base, unsigned device,
- unsigned address);
-int do_smbus_write_byte(unsigned smbus_base, unsigned device,
- unsigned address, unsigned data);
+int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
+ unsigned int address);
+int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
+ unsigned int address, unsigned int data);
#endif
diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c
index 031d2bd..8d3a562 100644
--- a/src/soc/intel/broadwell/iobp.c
+++ b/src/soc/intel/broadwell/iobp.c
@@ -23,7 +23,7 @@
static inline int iobp_poll(void)
{
- unsigned try;
+ unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
u16 status = RCBA16(IOBPS);
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 06c92c3..800e8ba 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -149,7 +149,7 @@
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -189,7 +189,7 @@
static int mei_send_packet(struct mei_header *mei, void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write */
@@ -293,8 +293,8 @@
{
struct mei_header mei_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index c3d9e13..3fb60e8 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -186,7 +186,7 @@
static void pch_pcie_device_set_func(int index, int pci_func)
{
device_t dev;
- unsigned new_devfn;
+ unsigned int new_devfn;
dev = rpc.ports[index];
@@ -638,7 +638,8 @@
root_port_commit_config();
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(device_t dev, unsigned int vendor,
+ unsigned int device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device)
diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
index 9c0feea..13fdaf6 100644
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ b/src/soc/intel/broadwell/romstage/smbus.c
@@ -44,7 +44,7 @@
reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
}
diff --git a/src/soc/intel/broadwell/smbus_common.c b/src/soc/intel/broadwell/smbus_common.c
index 26bb4fd..e392f40 100644
--- a/src/soc/intel/broadwell/smbus_common.c
+++ b/src/soc/intel/broadwell/smbus_common.c
@@ -32,7 +32,7 @@
static int smbus_wait_until_ready(u16 smbus_base)
{
- unsigned loops = SMBUS_TIMEOUT;
+ unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@@ -45,7 +45,7 @@
static int smbus_wait_until_done(u16 smbus_base)
{
- unsigned loops = SMBUS_TIMEOUT;
+ unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
@@ -56,7 +56,8 @@
return loops ? 0 : -1;
}
-int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
+ unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
@@ -102,8 +103,8 @@
return byte;
}
-int do_smbus_write_byte(unsigned smbus_base, unsigned device,
- unsigned address, unsigned data)
+int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
+ unsigned int address, unsigned int data)
{
unsigned char global_status_register;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 7a7eaf7..ebcf93c 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -102,7 +102,7 @@
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
- unsigned databytes;
+ unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@@ -166,7 +166,7 @@
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -174,7 +174,7 @@
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -182,7 +182,7 @@
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned) addr & 0xffff) - 0xf020);
+ v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@@ -190,21 +190,21 @@
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned) addr & 0xffff) - 0xf020);
+ b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@@ -307,13 +307,13 @@
uint32_t offset;
} spi_transaction;
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
--
To view, visit https://review.coreboot.org/18873
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
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