[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block:[WIP] Create header for GPIO controll...
Hannah Williams (Code Review)
gerrit at coreboot.org
Sun Mar 19 02:08:00 CET 2017
Hannah Williams has uploaded a new change for review. ( https://review.coreboot.org/18892 )
Change subject: soc/intel/common/block:[WIP] Create header for GPIO controller config
......................................................................
soc/intel/common/block:[WIP] Create header for GPIO controller config
Change-Id: I09cc3df4749288d3772600915363549d731cebab
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
A src/soc/intel/common/block/include/intelblocks/gpio.h
1 file changed, 362 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/18892/2
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
new file mode 100644
index 0000000..3010441
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -0,0 +1,362 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_INTELBLOCKS_GPIO_H_
+#define _SOC_INTELBLOCKS_GPIO_H_
+
+#ifndef __ACPI__
+#include <types.h>
+
+/*
+ * GPIO_PADBAR_OFFSET
+ * starting address of Pad0 register sets within a Community
+ * It is meant for software to discover from where the very first Pad
+ * register (i.e. Pad0 register) starts to compute the next Pad
+ * address offsets
+ */
+#define PADBAR_MASK 0xffff
+
+/*
+ * GPIO_MISCCFG_OFFSET
+ * Assigns a specific GPIO Group to the ACPI GPE ( GPE0[95:64],
+ * GPE0[63:32] and ACPI GPE0[31:0])
+ */
+#define MISCCFG_GPE0_DW0_SHIFT 8
+#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
+#define MISCCFG_GPE0_DW1_SHIFT 12
+#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
+#define MISCCFG_GPE0_DW2_SHIFT 16
+#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+
+/*
+ * GPIO_HOSTSW_OWN
+ * Host Software Pad Ownership 0 = ACPI Mode 1 = GPIO Driver Mode
+ */
+enum host_sw {
+ ACPI_D = 0, // ACPI driver
+ GPIO_D = 1, // GPIO driver
+};
+
+/*
+ * GPIO_PAD_CFG_DW0
+ */
+/* GPIOTXSTATE[0]: This is the current internal RX pad state */
+#define DW0_GPIOTXSTATE_BIT 0
+enum gpio_tx_state {
+ LO = 0,
+ HI = 1,
+ GPIO_TX_STATE_MASK = HI,
+};
+
+/* GPIORXSTATE[1]: 0 = Drive a level to the TX output pad*/
+#define DW0_GPIORXSTATE_BIT 1
+#define DW0_GPIORXSTATE_MASK 1
+
+/* GPIOTXDIS[9:8] Configure pad buffer */
+#define DW0_GPIO_CFG_BIT 8
+enum gpio_config_en {
+ NATIVE = 0xff,
+ GPIO = 0, /* Native, no need to set PAD_VALUE */
+ GPI = 1, /* GPI, input only in PAD_VALUE */
+ GPO = 2, /* GPO, output only in PAD_VALUE */
+ HI_Z = 3,
+ GPIO_CONFIG_MASK = HI_Z,
+};
+
+/* DW0_PMODE[n:10]: a value of 0 means this pad is used as a GPIO and any other
+ value would specify which Native function is muxed onto the pad
+ The number of valid modes is SOC dependent
+ */
+#define DW0_PMODE_BIT 10
+/* #define DW0_PMODE_MASK to be defined by soc/gpio.h */
+#define M(mode) (mode)
+
+/* GPIROUT[20:17]: when GPIO is in input mode, which interrupt type it
+ * is routed to */
+#define DW0_GPIROUT_BIT 17
+enum gpio_route {
+ GPIO_ROUT_IOAPIC = 8 ,
+ GPIO_ROUT_SCI = 4,
+ GPIO_ROUT_SMI = 2,
+ GPIO_ROUT_NMI = 1,
+ GPIO_ROUT_NONE = 0,
+ GPIO_ROUT_MASK = 0xF,
+};
+
+/* RXTXENCFG[22:21]: Specifies if the Native function controls RX and TX buffer
+ Not applicable when Pad Mode is 0 (i.e.GPIO mode)
+ This is reserved in some SOCs
+ */
+#define DW0_RXTXENCFG_BIT 21
+enum native_pad_config {
+ TXEN_RXEN = 0,
+ TXEN_RXDIS_RX0 = 1,
+ TXEN_RXDIS_RX1 = 2,
+ TXEN_RXEN_ALWAYS = 3,
+ NATIVE_PAD_CONFIG_MASK = TXEN_RXEN_ALWAYS
+};
+
+/*
+ * RXINV[23]: This bit determines if the selected pad state should go through
+ * the polarity inversion stage.This field is only applicable when the
+ * RX buffer is configured as an input in either GPIO Mode or native function
+ * mode.The polarity inversion takes place at the mux node of raw vs filtered
+ * or non-filtered RX pad state as determined by PreGfRXsel and RXPadStSel
+ */
+#define DW0_RXINV_BIT 23
+enum invert_rx {
+ NO_INVERT = 0,
+ INVERT = 1,
+ INVERT_RX_MASK = INVERT,
+};
+
+/*
+ * PREGFRXSEL[24]: 0 = Select synchronized, non filtered RX pad state
+ * 1 = Select synchronized, filtered RX pad state
+ * NOT available in all SOCs
+ */
+#define DW0_PREGFRXSEL_BIT 24
+enum rx_glitch_filter {
+ RX_GLITCH_FILTER_DIS = 0,
+ RX_GLITCH_FILTER_EN = 1,
+ RX_GLITCH_FILTER_MASK = RX_GLITCH_FILTER_EN
+};
+
+/*
+ * RXEVCFG[26:25]: Determines how the interrupt or wake triggering events
+ * should be delivered to the GPIO Community Controller - as is, as a pulse,
+ * or level signal
+ */
+#define DW0_RXEVCFG_BIT 25
+enum interrupt_type {
+ LEVEL = 0,
+ EDGE = 1,
+ INT_DIS = 2,
+ BOTHEDGE = 3,
+ INT_TYPE_MASK = BOTHEDGE,
+};
+
+/*
+ * PADRSTCFG[31:30]: controls which reset is used to reset GPIO pad
+ * register fields
+ */
+#define DW0_PADRSTCFG_BIT 30
+enum pad_reset_cfg {
+ RESET_POWERGOOD,
+ RESET_DEEP,
+ RESET_PLTRST,
+ RESET_CONFIG_MASK
+};
+
+/*
+ * INTSEL[7:0]: which interrupt line driven from the GPIO Controller toggles when an
+ * interrupt is detected on this pad 0 = Interrupt Line 0 to max IOxAPIC IRQ
+ * supported
+ */
+#define DW1_INTSEL_BIT 0
+#define DW1_INTSEL_MASK 0xFF
+/*
+ * IOSTERM[9:8]: defines the behaviour of the termination logic when the
+ * IO Standby state has been triggered
+ */
+#define DW1_IOSTERM_BIT 8
+enum iosterm {
+ SAME = 0, /* Same as functional pull */
+ DISPUPD = 1, /* Disable Pullup and Pulldown */
+ ENPD = 2, /* Enable Pulldown */
+ ENPU = 3, /* Enable Pullup */
+ IOSTERM_MASK = ENPU
+};
+
+/*
+ * TERM[13:10]: Pad Termination defines the different weak pull-up and pull-down
+ * settings supported by the buffer
+ */
+#define DW1_TERM_BIT 10
+enum term_type {
+ P_NONE = 0, ///< Pull None
+ P_5K_L = 2, ///< Pull Down 5K
+ P_20K_L = 4, ///< Pull Down 20K
+ P_1K_H = 9, ///< Pull Up 1K
+ P_2K_H = 11, ///< Pull Up 2K
+ P_20K_H = 12, ///< Pull Up 20K
+ P_5K_H = 10, ///< Pull Up 5K
+ P_1K2K_H = 13, ///< Pull Up 1K
+ NATIVE_CONTROL = 15
+};
+
+/*
+ * IOSSTATE[17:14]: defines which state the pad should be parked in when the
+ * I/O is in a standby state
+ */
+#define DW1_IOSSTATE_BIT 14
+enum ios_state {
+ LAST_VALUE = 0, /* Latch last value driven on TX,
+ TX Enable and RX Enable*/
+ D0RXDRX0I = 1, /* Drive 0 with RX disabled and
+ RX drive 0 internally*/
+ D0RXDRX1I = 2, /* Drive 0 with RX disabled and RX drive 1
+ internally*/
+ D1RXDRX0I = 3, /* Drive 1 with RX disabled and RX drive 0
+ internally*/
+ D1RXDRX1I = 4, /* Drive 1 with RX disabled and RX drive 1
+ internally*/
+ D0RXE = 5, /* Drive 0 with RX enabled*/
+ D1RXE = 6, /* Drive 1 with RX enabled*/
+ HIZRX0I = 7, /* Hi-Z with RX drive 0 internally*/
+ HIZRX1I = 8, /* Hi-Z with RX drive 1 internally*/
+ TXDRXE = 9, /* TX Disabled and RX Enabled
+ (i.e. wake or interrupt)*/
+ IOS_MASK = 15, /* IO Standby signal is masked for this pad*/
+};
+
+#define NA 0xFF
+
+
+#define GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_config) \
+ ((((interrupt_type ) != NA) ? \
+ (interrupt_type & INT_TYPE_MASK) << DW0_RXEVCFG_BIT : INT_DIS \
+ << DW0_RXEVCFG_BIT ) | \
+ ((rx_invert != NA) ? \
+ (rx_invert & INVERT_RX_MASK) << DW0_RXINV_BIT : \
+ NO_INVERT << DW0_RXINV_BIT) | \
+ ((gpi_rout != NA) ? \
+ ((gpi_rout & GPIO_ROUT_MASK) << DW0_GPIROUT_BIT) : \
+ GPIO_ROUT_NONE << DW0_GPIROUT_BIT) | \
+ ((pmode & PAD_MODE_MASK) << DW0_PMODE_BIT) | \
+ ((gpio_config != NA) ? \
+ ((gpio_config & GPIO_CONFIG_MASK) << DW0_GPIO_CFG_BIT ): \
+ 0 << DW0_GPIO_CFG_BIT) | \
+ ((gpo_state != NA) ? \
+ (gpo_state & GPIO_TX_STATE_MASK) : 0) | \
+ ((pad_reset_config != NA) ? \
+ ((pad_reset_config & RESET_CONFIG_MASK) << DW0_PADRSTCFG_BIT) \
+ : 0))
+
+#define GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term) \
+ (((ios_state != NA) ? \
+ ((ios_state & IOS_MASK) << DW1_IOSSTATE_BIT) : LAST_VALUE) | \
+ ((term_H_L != NA) ? \
+ ((term_H_L & NATIVE_CONTROL) << DW1_TERM_BIT) : P_NONE) | \
+ ((ios_term != NA) ? \
+ ((ios_term & IOSTERM_MASK) << DW1_IOSTERM_BIT) : SAME))
+
+typedef uint32_t gpio_t;
+
+struct pad_config {
+ int pad;/* offset of pad within community */
+ uint32_t pad_config0;
+ uint32_t pad_config1;
+ int hostsw; /* ACPI or GPIO driver */
+ int wake_enabled; /*Wake enable for direct IRQ pin*/
+ const char *pad_name;
+};
+
+#define GLK_GPIO_PAD_CONF(pad_name, pad_offset, pmode, gpio_config, host_sw, gpo_state, interrupt_type, wake_enabled, term_H_L, rx_invert, gpi_rout, ios_state, ios_term, pad_reset_cfg, community ) \
+ { \
+ pad_offset, \
+ GLK_GPIO_PAD0_CONF(interrupt_type, rx_invert, gpi_rout, pmode, gpio_config, gpo_state, pad_reset_cfg), \
+ GLK_GPIO_PAD1_CONF(ios_state, term_H_L, ios_term), \
+ community, \
+ ((host_sw == NA)||(host_sw == ACPI_D))? ACPI_D : GPIO_D,\
+ wake_enabled, \
+ pad_name, \
+ }
+
+typedef uint32_t(*gpio_config_read)(int pad, int reg_offset);
+typedef void(*gpio_config_write)(int pad, int reg_offset, uint32_t value);
+
+/* This list must be in order, from highest pad numbers, to lowest pad numbers*/
+struct pad_community {
+ uint16_t first_pad; /* first pad in community */
+ uint16_t last_pad; /* last pad in community */
+ uint8_t port;
+ uint8_t num_gpi_grps; /* number of groups in community */
+ uint8_t gpi_offset;
+ gpio_config_read read_fn; /* override read access function if different
+ from default */
+ gpio_config_write write_fn;/* override read access function if
+ different from default */
+ const char *name;
+};
+
+/* Max possible 32 bit GPI status registers is 4 */
+#define NUM_GPI_STATUS_REGS 4
+
+/*
+ * Structure to represent GPI status for GPE and SMI. Use helper
+ * functions for interrogating particular GPIs.
+ */
+struct gpi_status {
+ uint32_t grp[NUM_GPI_STATUS_REGS];
+};
+
+
+/*
+ * Returns GPIO community map for specified pad
+ */
+const struct pad_community *soc_gpio_get_community(gpio_t pad);
+
+/*
+ * Returns number of gpio communities
+ */
+int soc_gpio_get_num_communities(void);
+
+/*
+ * Clear GPI SMI status and fill in the structure representing enabled
+ * and set status.
+ */
+void gpi_clear_get_smi_status(struct gpi_status *sts);
+
+/* Return 1 if gpio is set in the sts. Otherwise 0. */
+int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
+
+/*
+ * Configuration for raw pads. Some pads are designated as only special function
+ * pins, and don't have an associated GPIO number, so we need to expose the raw
+ * pad configuration functionality.
+ */
+void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
+
+/*
+ * Calculate Address of DW0 register for given GPIO
+ */
+void * gpio_dwx_address(const gpio_t pad);
+
+/*
+ * Returns the gpio group number
+ */
+int soc_gpe_route_to_gpio(int route);
+
+/*
+ * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
+ * are passed which is then mapped to proper groups for MISCCFG. This basically
+ * sets the MISCCFG register bits:
+ * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
+ * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
+ * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
+ */
+void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d);
+
+/*
+ * Handle any ITSS specific configuration
+ */
+void gpio_configure_itss(const struct pad_config *cfg,
+ uint16_t port, gpio_t pad_cfg_offset);
+
+#endif
+
+#endif /* _SOC_INTELBLOCKS_GPIO_H_ */
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I09cc3df4749288d3772600915363549d731cebab
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
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