[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use C entry code for MTRR programming
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon Mar 20 16:21:44 CET 2017
Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/18923 )
Change subject: soc/intel/skylake: Use C entry code for MTRR programming
......................................................................
soc/intel/skylake: Use C entry code for MTRR programming
Make skylake cache as ram SPI mapped MTRR programming
align with apollolake code.
Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/cache_as_ram.S
M src/soc/intel/skylake/bootblock/cpu.c
3 files changed, 31 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/18923/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 2a6b152..3a5a024 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -21,6 +21,7 @@
bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
bootblock-y += gpio.c
+bootblock-y += mmap_boot.c
bootblock-y += monotonic_timer.c
bootblock-y += pch.c
bootblock-y += pcr.c
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S
index 3f8f0f0..53ddeda 100644
--- a/src/soc/intel/skylake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S
@@ -242,52 +242,16 @@
wrmsr
post_code(0x27)
- /*
- * Configure the BIOS code region as write-protected (WP) cacheable
- * memory type using a single variable range MTRR.
- *
- * Ensure region to cache meets MTRR requirements for
- * size and alignment.
- */
- movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
- movl $CONFIG_ROM_SIZE, %eax /* Code region size */
- cmpl $0, %edi
- jz .halt_forever
- cmpl $0, %eax
- jz .halt_forever
-
- post_code(0x28)
- /*
- * Program base register
- */
- xorl %edx, %edx /* clear upper dword */
- movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */
- movl %edi, %eax
- orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */
- wrmsr
-
- movl $CONFIG_ROM_SIZE, %eax
-
- /*
- * Compute MTRR mask value: Mask = NOT (Size - 1)
- */
- dec %eax /* eax - size to cache less one byte */
- not %eax /* eax contains low 32 bits of mask */
- or $MTRR_PHYS_MASK_VALID, %eax
- /*
- * Program mask register
- */
- movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */
- movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
- wrmsr
car_init_done:
- post_code(0x29)
+ post_code(0x28)
/* Setup bootblock stack */
mov $_car_stack_end, %esp
+ post_code(0x29)
+
/*push TSC value to stack*/
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index c6ede53..7fbc72d 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -18,11 +18,14 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode/microcode.c>
#include <reset.h>
+#include <lib.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
+#include <soc/mmap_boot.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/spi.h>
@@ -101,8 +104,32 @@
soft_reset();
}
+static void cache_bios_region(void)
+{
+ int mtrr;
+ size_t rom_size;
+ uint32_t alignment;
+
+ mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ /* Only the IFD BIOS region is memory mapped (at top of 4G) */
+ rom_size = get_bios_size();
+
+ if (!rom_size)
+ return;
+
+ /* Round to power of two */
+ alignment = 1 << (log2_ceil(rom_size));
+ rom_size = ALIGN_UP(rom_size, alignment);
+ set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
+}
+
void bootblock_cpu_init(void)
{
+ cache_bios_region();
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
intel_update_microcode_from_cbfs();
--
To view, visit https://review.coreboot.org/18923
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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