[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mp_init.c: Removed hard coded timeout in bsp_do_flig...

[Anonymous Coward (Code Review)]

Anonymous Coward #1001583 has uploaded a new change for review. ( https://review.coreboot.org/18931 )

Change subject: cpu/x86/mp_init.c: Removed hard coded timeout in bsp_do_flight_plan
......................................................................

cpu/x86/mp_init.c: Removed hard coded timeout in bsp_do_flight_plan

This fix removes hard coded and const. timeout in bsp_do_flight_plan,
which doesn't take into account:
 - cores numer
 - log level
 - TTS0 baud rate
The old value = 100ms is not enought in case of more than 8 cores
is used during debug session with high log level.
New timeout has become dependent on these stuff.

Change-Id: Ic0787009e8286b13bc76f763758e42aa6d6782d4
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak at intel.com>
---
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/mp.h
2 files changed, 10 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/18931/1

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 61f153e..8f46a5b 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2017 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -532,8 +533,8 @@
 {
 	int i;
 	int ret = 0;
-	const int timeout_us = 100000;
-	const int step_us = 100;
+	const int timeout_us = MP_TIMEOUT_US;
+	const int step_us = MP_TIMEOUT_STEP_US;
 	int num_aps = mp_params->num_cpus - 1;
 
 	for (i = 0; i < mp_params->num_records; i++) {
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index 0671b62..d4efc2b 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2017 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +22,12 @@
 
 #define CACHELINE_SIZE 64
 
+#define MP_MOD (1 + (CONFIG_MAX_CPUS > 8)\
+	+ (CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 4))
+#define MP_BAUD_MOD ((CONFIG_TTYS0_BAUD > 115200) + 115200 / CONFIG_TTYS0_BAUD)
+#define MP_TIMEOUT_US (100000 * MP_MOD * MP_BAUD_MOD)
+#define MP_TIMEOUT_STEP_US 100
+
 struct cpu_info;
 struct bus;
 

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic0787009e8286b13bc76f763758e42aa6d6782d4
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Anonymous Coward #1001583