[coreboot-gerrit] Change in coreboot[master]: northbridge/via/cn700: Add some delays during raminit
Martin Roth (Code Review)
gerrit at coreboot.org
Wed Mar 22 18:40:00 CET 2017
Martin Roth has posted comments on this change. ( https://review.coreboot.org/18893 )
Change subject: northbridge/via/cn700: Add some delays during raminit
......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/18893/1//COMMIT_MSG
Commit Message:
PS1, Line 13: regisers
registers.
https://review.coreboot.org/#/c/18893/1/src/northbridge/via/cn700/raminit.c
File src/northbridge/via/cn700/raminit.c:
PS1, Line 65: udelay(200);
: pci_write_config8(dev, 0x50, 0x88);
I'm not really crazy about this since it affects other mainboards as well. Maybe make a separate function that enables / disables the delay based on a Kconfig option?
void c7_pci_write_config8 (pci_devfn_t dev, u8 reg, u8 val)
{
if IS_ENABLED(CONFIG_C7_CPU_DELAY)
udelay(200)
pci_write_config8(dev, rev, val);
}
Add C7_CPU_DELAY to via/cn700/Kconfig
config C7_CPU_DELAY
def_bool n
help
At least one board needs delays between PCI writes when
configuring the CPU or it locks up.
Then in the Kconfig for your board:
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select C7_CPU_DELAY
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lubomir Rintel <lkundrak at v3.sk>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: Yes
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