[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
Aamir Bohra (Code Review)
gerrit at coreboot.org
Mon Mar 27 15:53:47 CEST 2017
Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19001 )
Change subject: soc/intel/skylake: Clean up serialio header file.
......................................................................
soc/intel/skylake: Clean up serialio header file.
Move and rename I2C and UART specific macro definitions
under serialio.h to i2c.h and uart.h respectively.
Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/soc/intel/skylake/bootblock/i2c.c
M src/soc/intel/skylake/bootblock/uart.c
A src/soc/intel/skylake/include/soc/i2c.h
M src/soc/intel/skylake/include/soc/serialio.h
A src/soc/intel/skylake/include/soc/uart.h
5 files changed, 66 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19001/1
diff --git a/src/soc/intel/skylake/bootblock/i2c.c b/src/soc/intel/skylake/bootblock/i2c.c
index 11d145c..0401d3b 100644
--- a/src/soc/intel/skylake/bootblock/i2c.c
+++ b/src/soc/intel/skylake/bootblock/i2c.c
@@ -22,7 +22,7 @@
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/bootblock.h>
-#include <soc/serialio.h>
+#include <soc/i2c.h>
#include "chip.h"
uintptr_t lpss_i2c_base_address(unsigned int bus)
@@ -77,10 +77,9 @@
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take device out of reset */
- reg = (void *)(base + SIO_REG_PPR_RESETS);
+ reg = (void *)(base + I2C_RESET);
value = read32(reg);
- value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
- SIO_REG_PPR_RESETS_IDMA;
+ value |= I2C_RESET_EN | I2C_RESET_DMA_EN;
write32(reg, value);
/* Initialize the controller */
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index ff1687c..4889428 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -22,7 +22,7 @@
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
-#include <soc/serialio.h>
+#include <soc/uart.h>
#include <gpio.h>
/* UART2 pad configuration. Support RXD and TXD for now. */
@@ -46,21 +46,20 @@
pci_write_config32(dev, PCI_COMMAND, tmp);
/* Take UART2 out of reset */
- tmp = read32(base + SIO_REG_PPR_RESETS);
- tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
- SIO_REG_PPR_RESETS_IDMA;
- write32(base + SIO_REG_PPR_RESETS, tmp);
+ tmp = read32(base + UART_RESET);
+ tmp |= UART_RESET_EN | UART_RESET_DMA_EN;
+ write32(base + UART_RESET, tmp);
/*
* Set M and N divisor inputs and enable clock.
* Main reference frequency to UART is:
* 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
*/
- tmp = read32(base + SIO_REG_PPR_CLOCK);
- tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
- (SIO_REG_PPR_CLOCK_N_DIV << 16) |
- (SIO_REG_PPR_CLOCK_M_DIV << 1);
- write32(base + SIO_REG_PPR_CLOCK, tmp);
+ tmp = read32(base + UART_CLK);
+ tmp |= UART_CLK_EN | UART_CLK_UPDATE |
+ UART_CLK_DIV_N(UART_CLK_N_VAL) |
+ UART_CLK_DIV_M(UART_CLK_M_VAL);
+ write32(base + UART_CLK, tmp);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
diff --git a/src/soc/intel/skylake/include/soc/i2c.h b/src/soc/intel/skylake/include/soc/i2c.h
new file mode 100644
index 0000000..b2d24fd
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/i2c.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_SKYLAKE_I2C_H
+#define SOC_SKYLAKE_I2C_H
+
+#define I2C_RESET 0x204
+#define I2C_RESET_EN (3 << 0)
+#define I2C_RESET_DMA_EN (1 << 2)
+
+#endif /* SOC_SKYLAKE_I2C_H */
diff --git a/src/soc/intel/skylake/include/soc/serialio.h b/src/soc/intel/skylake/include/soc/serialio.h
index d66bf80..a07f29c 100644
--- a/src/soc/intel/skylake/include/soc/serialio.h
+++ b/src/soc/intel/skylake/include/soc/serialio.h
@@ -17,17 +17,6 @@
#ifndef _SERIALIO_H_
#define _SERIALIO_H_
-#define SIO_REG_PPR_CLOCK 0x200
-#define SIO_REG_PPR_CLOCK_EN (1 << 0)
-#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
-#define SIO_REG_PPR_CLOCK_N_DIV 0xc35
-#define SIO_REG_PPR_CLOCK_M_DIV 0x30
-
-#define SIO_REG_PPR_RESETS 0x204
-#define SIO_REG_PPR_RESETS_FUNC (1 << 0)
-#define SIO_REG_PPR_RESETS_APB (1 << 1)
-#define SIO_REG_PPR_RESETS_IDMA (1 << 2)
-
typedef enum {
PchSerialIoDisabled,
PchSerialIoAcpi,
diff --git a/src/soc/intel/skylake/include/soc/uart.h b/src/soc/intel/skylake/include/soc/uart.h
new file mode 100644
index 0000000..e660ab0
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/uart.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_SKYLAKE_UART_H
+#define SOC_SKYLAKE_UART_H
+
+#define UART_CLK 0x200
+#define UART_CLK_UPDATE (1 << 31)
+#define UART_CLK_EN (1 << 0)
+#define UART_CLK_N_VAL 0xc35
+#define UART_CLK_M_VAL 0x30
+#define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+#define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+
+#define UART_RESET 0x204
+#define UART_RESET_EN (3 << 0)
+#define UART_RESET_DMA_EN (1 << 2)
+
+#endif /* SOC_SKYLAKE_UART_H */
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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