[coreboot-gerrit] Change in coreboot[master]: drivers/storage: Add SDHCI debug support
Lee Leahy (Code Review)
gerrit at coreboot.org
Mon Mar 27 21:40:01 CEST 2017
Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/19012 )
Change subject: drivers/storage: Add SDHCI debug support
......................................................................
drivers/storage: Add SDHCI debug support
Display the bus width and speed.
TEST=Build and run on reef
Change-Id: Ic594b6bbd10a9509f4194c72134ae8a875b4ae47
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
M src/drivers/storage/Kconfig
M src/drivers/storage/mmc.c
M src/drivers/storage/sdhci.c
3 files changed, 39 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/19012/1
diff --git a/src/drivers/storage/Kconfig b/src/drivers/storage/Kconfig
index 2546eea..5774843 100644
--- a/src/drivers/storage/Kconfig
+++ b/src/drivers/storage/Kconfig
@@ -31,4 +31,10 @@
help
Display MMC commands and responses
+config SDHCI_DEBUG
+ bool "Debug SD/MMC host controller"
+ default n
+ help
+ Display clock speed and bus width settings
+
endif # DRIVERS_STORAGE
diff --git a/src/drivers/storage/mmc.c b/src/drivers/storage/mmc.c
index 62ebff3..6d81103 100644
--- a/src/drivers/storage/mmc.c
+++ b/src/drivers/storage/mmc.c
@@ -578,6 +578,8 @@
mmc_error("switch to bus width for hs400es failed\n");
return ret;
}
+ if (IS_ENABLED(SDHCI_DEBUG))
+ printf("SD/MMC bus switching to DDR\n");
/* Adjust Host Bus With to 8-bit */
mmc_set_bus_width(media->ctrlr, 8);
diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c
index be06940..af5d162 100644
--- a/src/drivers/storage/sdhci.c
+++ b/src/drivers/storage/sdhci.c
@@ -407,11 +407,16 @@
{
unsigned int div, clk, timeout;
+ /* Turn off the clock */
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
- if (clock == 0)
+ if (clock == 0) {
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC bus clock: Off\n");
return 0;
+}
+ /* Compute the divisor for the new clock frequency */
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
if (host->clock_base <= clock)
@@ -436,6 +441,12 @@
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Display the requested clock frequency */
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC bus clock: %d.%03d MHz\n",
+ clock / 1000000,
+ (clock / 1000) % 1000);
/* Wait max 20 ms */
timeout = 20;
@@ -494,20 +505,28 @@
if (power != (unsigned short)-1) {
switch (1 << power) {
case MMC_VDD_165_195:
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC voltage: 1.8 Volts\n");
pwr = SDHCI_POWER_180;
break;
case MMC_VDD_29_30:
case MMC_VDD_30_31:
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC voltage: 3.0 Volts\n");
pwr = SDHCI_POWER_300;
break;
case MMC_VDD_32_33:
case MMC_VDD_33_34:
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC voltage: 3.3 Volts\n");
pwr = SDHCI_POWER_330;
break;
}
}
if (pwr == 0) {
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC voltage: Off\n");
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
return;
}
@@ -573,15 +592,23 @@
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc_ctrlr->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
- if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
+ if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
ctrl |= SDHCI_CTRL_8BITBUS;
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC bus width: 8 bits\n");
+ }
} else {
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
- if (mmc_ctrlr->bus_width == 4)
+ if (mmc_ctrlr->bus_width == 4) {
ctrl |= SDHCI_CTRL_4BITBUS;
- else
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC bus width: 4 bits\n");
+ } else {
ctrl &= ~SDHCI_CTRL_4BITBUS;
+ if (IS_ENABLED(CONFIG_SDHCI_DEBUG))
+ printf("SD/MMC bus width: 1 bit\n");
+ }
}
if (!(mmc_ctrlr->timing == MMC_TIMING_LEGACY) &&
--
To view, visit https://review.coreboot.org/19012
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic594b6bbd10a9509f4194c72134ae8a875b4ae47
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy at intel.com>
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