Unified setup...

[Stefan Reinauer]

* YhLu <YhLu at tyan.com> [030828 23:36]:
> PS: 
> -        PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00ff0000,
> +        PCI_ADDR(0, 0x18, 0, 0x94), 0xff0000ff, 0x00050000,
> [..]
> -        PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00000000,
> +        PCI_ADDR(0, 0x18, 0, 0xd4), 0xff0000ff, 0x00030000,
> 
> should be there. It defines the bus number behind the links. It will be used
> when enumerating the non-coherent devices.

I agree. But maybe we find a nicer way of describing this.

Are these "hard coded" in hardware? 
The motherboard configuration should then probably contain a busnumber
value for each ht bridge that implements a pci bus

southbridge amd/amd8131 "amd8131"
        register "bus0" = "5"
end

southbridge amd/amd8151 "amd8151"
        register "bus0" = "3"
end

Or should this be handled distinct from the bridges with 
options like
option BUS1=99
option BUS2=5
?


Stefan

-- 
Architecture Team
    SuSE Linux AG