DDR SDRAM Initialization.
Eric W. Biederman
ebiederman at lnxi.com
Thu Jan 16 14:30:00 CET 2003
sivakumar <sivakumar.subramani at wipro.com> writes:
> Thanks for the information.
>
> I have gone through the code and have following query.
> Following is the one of the step in Initialization of DDR SDRAM.
>
> -Next a MODE REGISTER SET command should be issued for the Extended
> Mode Register to enable the DLL,
>
> /* 5. Issue EMRS to enable DLL */
> SET_RAM_COMMAND(RAM_COMMAND_EMRS)
> movl (0x0000<<MD_SHIFT), %eax
> DO_DELAY
>
> First we are setting the Mode select bit of DRAM controller Mode
> Register to Extended Mode Register Set Enable.
>
> >From DDR spec, it is given that zero bit of EMRS will enable the DLL.
>
> Here I want to know how by moving the (0x0000 << MD_SHIFT) to eax
> register, we are writting to Extended mode register.
>
> Can any one explain this?
It is performing a memory read. A memory read in intel chipsets
when the command register is set properly causes commands to be sent
to memory. Reads seem to work a little bit more reliably than writes
in my experience.
Eric
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