EPIA-M DDR ram init progress

[Dave Ashley]

As a recap I was trying to get 2 specific DDR modules working with the
epia-m. One has ICT chips and the other has GET chips. The ICT module works
with the hardcoded dram configuration, but the GET module doesn't.
ICT = 1 bank 128M colbits = 10
GET = 2 banks 64M colbits = 9

I had tried hardcoding the dram settings to the ones award bios uses for the
GET module, but it wasn't working. I figured out what the problem was.
I need to do the ddr setup for each bank on the ddr module, not just the
first one. The hardcoded settings correspond to a ddr with just a single bank.

SPD contents is very easy to access. The epia-m code is including
src/northbridge/via/vt8623/raminit.inc
to initialize ram. I found problems with this, the jedec ddr init spec
sequence calls for reads of the ddr memory, this source actually does some
writes.

I'm wondering what the preferred way of implementing spd for epia-m would
be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put
that code in with the epia-m code, mix it with the smbus SPD read code,
and leave the result in the epia-m tree? Or should I modify the
src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that
can work since the SMBUS/SPD is accessed with the vt8235 registers, but the
DDR dram control registers are part of the northbridge.

I can rebuild linuxbios to have it work hardcoded for either memory module
type and it works fine, and I can probably live with this state until
someone else gets SPD working if it might happen within a month or two.
Otherwise I'll probably have to tackle it myself.

VIA's Bios porting guide for the nortbridge on the epia-m seems very
explicit on how to configure the ddr memory based on the SPD settings.
Implementing it should just be a matter of grinding through their flow charts.
It's simplified because it only has to deal with DDR memory.

-Dave