EPIA-M DDR ram init progress

[Andrew Ip]

Hi Dave,

> As a recap I was trying to get 2 specific DDR modules working with the
> epia-m. One has ICT chips and the other has GET chips. The ICT module works
> with the hardcoded dram configuration, but the GET module doesn't.
> ICT = 1 bank 128M colbits = 10
> GET = 2 banks 64M colbits = 9
Same here, but if I set 0x58 to 0xc0, both works.

> I had tried hardcoding the dram settings to the ones award bios uses for the
> GET module, but it wasn't working. I figured out what the problem was.
> I need to do the ddr setup for each bank on the ddr module, not just the
> first one. The hardcoded settings correspond to a ddr with just a single bank.
That's right because EPIA-M has only 1 ddr bank.  If some custom has more
that 1 bank, I can check it.

> SPD contents is very easy to access. The epia-m code is including
> src/northbridge/via/vt8623/raminit.inc
> to initialize ram. I found problems with this, the jedec ddr init spec
> sequence calls for reads of the ddr memory, this source actually does some
> writes.
Thanks for the catch.  It has been fixed.  The funny thing is writes work,
too!!!

> I'm wondering what the preferred way of implementing spd for epia-m would
> be. Should instead of including src/northbridge/via/vt8623/raminit.inc I put
> that code in with the epia-m code, mix it with the smbus SPD read code,
> and leave the result in the epia-m tree? Or should I modify the
> src/northbridge/via/vt8623/raminit.inc file directly? I don't see how that
> can work since the SMBUS/SPD is accessed with the vt8235 registers, but the
> DDR dram control registers are part of the northbridge.
SMBUS/SPD should be in southbridge like other platforms.  Then, mainboard's
Config can include those code such that raminit.inc can call later.  E7500
is a very nice reference.

-Andrew

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Andrew Ip
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