Flashing Bios Success...

[Peter Stuge]

On Thu, May 08, 2003 at 11:30:19AM -0600, Nathanael Noblet wrote:
> On Thursday, May 8, 2003, at 10:56  AM, Peter Stuge wrote:
> >
> >Memory chips are identified by first entering the software-id mode:
> >Write 0xaah to address 0x5555h in the ROM.
> >Write 0x55h to address 0x2aaah in the ROM.
> >Write 0x90h to address 0x5555h in the ROM.
> >
> >Now the 'manufacturer ID' and the 'device ID' bytes can be read from
> >addresses 0 and 1 in the ROM, respectively.
> >
> >After reading the IDs, exit software-id mode thusly:
> >Write 0xaah to address 0x5555h in the ROM.
> >Write 0x55h to address 0x2aaah in the ROM.
> >Write 0xf0h to address 0x5555h in the ROM.
> 
> I have these, the problem is in detecting the flash in the first place, 
> these sequences of commands don't return what they should. Ron is 
> telling me this is because the write enable bit isn't set.

Exactly, three writes to the chip are required before the ID can be read.
Without write enable signals flying the right way, no ID will be found.
(Reading the ID is how the flash is "detected".)


> So I now 
> have the docks for the SiS5595 that I didn't know I had (doesn't show 
> in lspci). So what I need to know is how to get access to the registers 
> in the SiS 5595 that set the write enable so that we can detect it 
> properly... and then all the JEDEC stuff would work.

Yep, I saw that you've got this down now. Excellent! :)


//Peter