[COMMIT] freebios2 How much have I broken?

Eric W. Biederman ebiederman at lnxi.com
Sat Oct 11 02:01:01 CEST 2003


This is a flush of all my pending Opteron bug fixes.
Plus a new version of romcc, with all of the outstanding changes.
Plus some very recent work on getting enables and disables of devices
  working properly.
Plus my reindenting/beautify tirad on the via epia code.

The guts look good but I suspect I have introduced some problems with
ports other than the hdama.  Especially with the configuration updates.
My apologies for not looking those up and fixing them but I need to go home,
and my queue of pending changes is far to long already.

Eric

- 1.1.5
  - O2, enums, and switch statements work in romcc
  - Support for compiling romcc on non x86 platforms
  - new romc options -msse and -mmmx for specifying extra registers to use
  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
  - Move the link specification to the chip specification instead of the path
  - Allow specifying devices with internal bridges.
  - Initial via epia support
  - Opteron errata fixes

VS: ----------------------------------------------------------------------
CVS: Enter Log.  Lines beginning with `CVS:' are removed automatically
CVS:
CVS: Committing in .
CVS:
CVS: Modified Files:
CVS:    NEWS src/arch/i386/config/make.base
CVS:    src/arch/i386/lib/console.inc src/arch/i386/lib/cpu.c
CVS:    src/boot/hardwaremain.c src/config/Config src/config/Config.lb
CVS:    src/config/Options.lb src/cpu/k8/cpufixup.c src/cpu/p6/mtrr.c
CVS:    src/devices/chip.c src/devices/device.c
CVS:    src/devices/device_util.c src/devices/hypertransport.c
CVS:    src/devices/pci_device.c src/devices/root_device.c
CVS:    src/include/cpu/k8/mtrr.h src/include/device/chip.h
CVS:    src/include/device/device.h src/include/device/path.h
CVS:    src/mainboard/amd/quartet/mptable.c
CVS:    src/mainboard/arima/hdama/Config
CVS:    src/mainboard/arima/hdama/Config.lb
CVS:    src/mainboard/arima/hdama/auto.c
CVS:    src/mainboard/arima/hdama/failover.c
CVS:    src/mainboard/arima/hdama/irq_tables.c
CVS:    src/mainboard/arima/hdama/mainboard.c
CVS:    src/mainboard/arima/hdama/mptable.c
CVS:    src/northbridge/amd/amdk8/Config
CVS:    src/northbridge/amd/amdk8/Config.lb
CVS:    src/northbridge/amd/amdk8/coherent_ht.c
CVS:    src/northbridge/amd/amdk8/misc_control.c
CVS:    src/northbridge/amd/amdk8/northbridge.c
CVS:    src/northbridge/amd/amdk8/raminit.c
CVS:    src/northbridge/via/vt8601/northbridge.c src/pc80/vgabios.c
CVS:    src/pc80/vgachip.h src/southbridge/amd/amd8111/Config.lb
CVS:    src/southbridge/amd/amd8111/amd8111_acpi.c
CVS:    src/southbridge/amd/amd8111/amd8111_early_smbus.c
CVS:    src/southbridge/amd/amd8111/amd8111_ide.c
CVS:    src/southbridge/amd/amd8111/amd8111_lpc.c
CVS:    src/southbridge/amd/amd8111/amd8111_usb.c
CVS:    src/southbridge/amd/amd8111/amd8111_usb2.c
CVS:    src/southbridge/amd/amd8131/amd8131_bridge.c
CVS:    src/southbridge/via/vt8231/chip.h
CVS:    src/southbridge/via/vt8231/vt8231.c
CVS:    src/southbridge/via/vt8231/vt8231_early_serial.c
CVS:    src/southbridge/via/vt8231/vt8231_early_smbus.c
CVS:    src/superio/NSC/pc87360/chip.h
CVS:    src/superio/NSC/pc87360/superio.c targets/buildtarget
CVS:    targets/arima/hdama/Config.lb util/newconfig/Makefile
CVS:    util/newconfig/config.g util/options/build_opt_tbl.c
CVS:    util/romcc/Makefile util/romcc/romcc.c
CVS:    util/romcc/tests/simple_test60.c
CVS: Added Files:
CVS:    src/northbridge/amd/amdk8/cpu_rev.c
CVS:    src/northbridge/amd/amdk8/mcf0_control.c
CVS:    src/southbridge/amd/amd8111/amd8111.c
CVS:    src/southbridge/amd/amd8111/amd8111.h
CVS:    src/southbridge/amd/amd8111/amd8111_ac97.c
CVS:    src/southbridge/amd/amd8111/amd8111_nic.c
CVS:    util/romcc/results/linux_test1.out
CVS:    util/romcc/results/linux_test2.out
CVS:    util/romcc/results/linux_test3.out
CVS:    util/romcc/results/linux_test4.out
CVS:    util/romcc/results/linux_test5.out
CVS:    util/romcc/results/linux_test6.out
CVS:    util/romcc/results/linux_test7.out
CVS:    util/romcc/tests/fail_test4.c util/romcc/tests/fail_test5.c
CVS:    util/romcc/tests/linux_console.h
CVS:    util/romcc/tests/linux_syscall.h
CVS:    util/romcc/tests/linux_test1.c util/romcc/tests/linux_test2.c
CVS:    util/romcc/tests/linux_test3.c util/romcc/tests/linux_test4.c
CVS:    util/romcc/tests/linux_test5.c util/romcc/tests/linux_test6.c
CVS:    util/romcc/tests/linux_test7.c
CVS:    util/romcc/tests/linuxi386_syscall.h
CVS:    util/romcc/tests/raminit_test6.c
CVS:    util/romcc/tests/simple_test57.c
CVS:    util/romcc/tests/simple_test58.c
CVS:    util/romcc/tests/simple_test61.c
CVS:    util/romcc/tests/simple_test62.c
CVS:    util/romcc/tests/simple_test63.c
CVS:    util/romcc/tests/simple_test64.c
CVS:    util/romcc/tests/simple_test65.c
CVS:    util/romcc/tests/simple_test66.c
CVS:    util/romcc/tests/simple_test67.c
CVS:    util/romcc/tests/simple_test68.c
CVS: ----------------------------------------------------------------------



More information about the coreboot mailing list