[COMMIT] Infrastructure Updates 4

[Stefan Reinauer]

* Eric W. Biederman <ebiederman at lnxi.com> [030903 17:47]:
> First the most basic result I have is that I need to know what all of the
> logical devices that come out of a chip are.
 
> So off of each logical device I have one or more channels.  The only
> way I could think of to describe multiple channels is to repeat
> the logical device in the configuration file. 
> 
> All of the logical device paths are relative to the device they are hanging
> off of (it just looks like the bus number).  So to say the amd/amd8131 was
> hanging off of the second hypertransport link I would change it's logical
> devices to:
> 
>          southbridge amd/amd8131 "amd8131"
>                  pci 1:0.0
>                  pci 1:0.1
>                  pci 1:1.0
>                  pci 1:1.1
>          end
> 
> I am not saying that is the best way to go, but it currently works.
 
Ah. this is fine and allows porting linuxbios easily to new opteron
mainboards.
I see some drawbacks:

* the logical devices of the amd8131 pci-x bridge has to be described in 
  the mainboard configuration file. This means a lot of duplicate config
  "code" spread over the mainboard directory. Can this somehow go to the
  Config.lb file in southbridge/amd/amd8131/ ?

* The device description itself and the link (channel?) information is
  intermixed (preventing above config change from happening)

* link information is duplicate. This might be a feature though when
  devices happen that connect to more than one link. (Is this
  theoretically possible, i.e. to raise bandwidth?)

> The register "up" is something that has not been used at all yet.  Personally
> I am not comfortable with the fact that we have both cpu and northbridge
> instances for the cpus..

This looks weird for the opteron case, true. But most architectures
still don't come with an on-cpu northbridge, so keeping that seperated
might be a good idea (in case a certain northbridge can cope with
several cpu types)

> > Does it look like this? :
> > 
> >    8111
> >      | 
> >    8131
> >      | 
> >    CPU0 -- CPU1
> 
> Yes.  The order of the device structures is significant.

should this:
 
        southbridge amd/amd8131 "amd8131"
                pci 0:0.0
                pci 0:0.1
                pci 0:1.0
                pci 0:1.1
        end
        southbridge amd/amd8111 "amd8111"
                pci 0:0.0
                pci 0:1.0
                [..]
        end

not rather look like this then: ?

        southbridge amd/amd8131 "amd8131"
                pci 0:0.0
                pci 0:0.1
                pci 0:1.0
                pci 0:1.1
                southbridge amd/amd8111 "amd8111"
                        pci 1:0.0
                        pci 1:1.0
                        [..]
                end
        end


> Yes.  Except I don't yet have a way to automatically down clock it from 800Mhz
> which it claims it can do but cannot.
 
this seems only like a matter of the information not being parsed from
an appropriate place in the config file yet.

> > Same thing applies for the 8151 that is used in the tyan and solo
> > boards. The link speed is currently written by
> > src/southbridge/amd/amd8151/amd8151_agp3.c
> > 
> > If the code is already covered by the new ht code it could be removed
> > from the 8151 code. 
> 
> Sounds good.

YhLu? Can you confirm that link speeds to AGP are ok without that code?
Does anyone have an appropriate method of testing the actual link speed
and/or width between any pair of devices?

Stefan

-- 
Architecture Team
    SuSE Linux AG