[LinuxBIOS] [PATCH] Rename E7520 -> e7520, E7525 -> e7525.

[Uwe Hermann]

Hi,

here's another cleanup patch. After applying it needs a few svn moves:

svn mv src/northbridge/intel/E7520 src/northbridge/intel/e7520
svn mv src/northbridge/intel/E7525 src/northbridge/intel/e7525

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
-------------- next part --------------
Index: src/mainboard/dell/s1850/Config.lb
===================================================================
--- src/mainboard/dell/s1850/Config.lb	(Revision 2475)
+++ src/mainboard/dell/s1850/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on 
 		chip southbridge/intel/i82801er # i82801er
 			# USB ports
Index: src/mainboard/dell/s1850/failover.c
===================================================================
--- src/mainboard/dell/s1850/failover.c	(Revision 2475)
+++ src/mainboard/dell/s1850/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/dell/s1850/auto.c
===================================================================
--- src/mainboard/dell/s1850/auto.c	(Revision 2475)
+++ src/mainboard/dell/s1850/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "s2850_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dai_g/Config.lb
===================================================================
--- src/mainboard/supermicro/x6dai_g/Config.lb	(Revision 2475)
+++ src/mainboard/supermicro/x6dai_g/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7525 # mch
+chip northbridge/intel/e7525 # mch
 	device pci_domain 0 on
 		chip southbridge/intel/esb6300  # esb6300 
 			register "pirq_a_d" = "0x0b0a0a05"
Index: src/mainboard/supermicro/x6dai_g/failover.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/failover.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dai_g/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7525/memory_initialized.c"
+#include "northbridge/intel/e7525/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/supermicro/x6dai_g/auto.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/auto.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dai_g/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7525/raminit.h"
+#include "northbridge/intel/e7525/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -19,7 +19,7 @@
 #include "watchdog.c"
 #include "reset.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7525/memory_initialized.c"
+#include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -50,7 +50,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7525/raminit.c"
+#include "northbridge/intel/e7525/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dhe_g/Config.lb
===================================================================
--- src/mainboard/supermicro/x6dhe_g/Config.lb	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520  # MCH
+chip northbridge/intel/e7520  # MCH
 	chip drivers/generic/debug  # DEBUGGING
 		device pnp 00.0 on end
 		device pnp 00.1 off end
Index: src/mainboard/supermicro/x6dhe_g/failover.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/failover.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/supermicro/x6dhe_g/auto.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/auto.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dhe_g2/failover.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/failover.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g2/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/supermicro/x6dhe_g2/auto.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/auto.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g2/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g2_fixups.c"
 #include "superio/nsc/pc87427/pc87427_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dhe_g2/Config.lb
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/Config.lb	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g2/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520  # MCH
+chip northbridge/intel/e7520  # MCH
 	chip drivers/generic/debug  # DEBUGGING
 		device pnp 00.0 off end
 		device pnp 00.1 off end
Index: src/mainboard/supermicro/x6dhe_g2/auto.updated.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/auto.updated.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhe_g2/auto.updated.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhe_g_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -68,7 +68,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dhr_ig/Config.lb
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/Config.lb	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on 
 		chip southbridge/intel/i82801er # i82801er
 			# USB ports
Index: src/mainboard/supermicro/x6dhr_ig/failover.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/failover.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/supermicro/x6dhr_ig/auto.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/auto.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhr_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/supermicro/x6dhr_ig2/Config.lb
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/Config.lb	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig2/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520 # mch
+chip northbridge/intel/e7520 # mch
 	device pci_domain 0 on 
 		chip southbridge/intel/i82801er # i82801er
 			# USB ports
Index: src/mainboard/supermicro/x6dhr_ig2/failover.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/failover.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig2/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/supermicro/x6dhr_ig2/auto.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/auto.c	(Revision 2475)
+++ src/mainboard/supermicro/x6dhr_ig2/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "reset.c"
 #include "x6dhr2_fixups.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 
@@ -69,7 +69,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 
 
Index: src/mainboard/intel/jarrell/failover.c
===================================================================
--- src/mainboard/intel/jarrell/failover.c	(Revision 2475)
+++ src/mainboard/intel/jarrell/failover.c	(Arbeitskopie)
@@ -9,7 +9,7 @@
 #include "arch/i386/lib/console.c"
 #include "pc80/mc146818rtc_early.c"
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 
 static unsigned long main(unsigned long bist)
 {
Index: src/mainboard/intel/jarrell/auto.c
===================================================================
--- src/mainboard/intel/jarrell/auto.c	(Revision 2475)
+++ src/mainboard/intel/jarrell/auto.c	(Arbeitskopie)
@@ -11,7 +11,7 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
-#include "northbridge/intel/E7520/raminit.h"
+#include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -20,7 +20,7 @@
 #include "power_reset_check.c"
 #include "jarrell_fixups.c"
 #include "superio/nsc/pc87427/pc87427_early_init.c"
-#include "northbridge/intel/E7520/memory_initialized.c"
+#include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
 #define SIO_GPIO_BASE 0x680
@@ -47,7 +47,7 @@
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/E7520/raminit.c"
+#include "northbridge/intel/e7520/raminit.c"
 #include "sdram/generic_sdram.c"
 #include "debug.c"
 
Index: src/mainboard/intel/jarrell/Config.lb
===================================================================
--- src/mainboard/intel/jarrell/Config.lb	(Revision 2475)
+++ src/mainboard/intel/jarrell/Config.lb	(Arbeitskopie)
@@ -132,7 +132,7 @@
 dir /pc80
 config chip.h
 
-chip northbridge/intel/E7520
+chip northbridge/intel/e7520
 	device pci_domain 0 on 
 		device pci 00.0 on end
 		device pci 00.1 on end
Index: src/northbridge/intel/E7520/pciexp_porta1.c
===================================================================
--- src/northbridge/intel/E7520/pciexp_porta1.c	(Revision 2475)
+++ src/northbridge/intel/E7520/pciexp_porta1.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7520/pciexp_portb.c
===================================================================
--- src/northbridge/intel/E7520/pciexp_portb.c	(Revision 2475)
+++ src/northbridge/intel/E7520/pciexp_portb.c	(Arbeitskopie)
@@ -8,7 +8,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7520/pciexp_portc.c
===================================================================
--- src/northbridge/intel/E7520/pciexp_portc.c	(Revision 2475)
+++ src/northbridge/intel/E7520/pciexp_portc.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7520/northbridge.c
===================================================================
--- src/northbridge/intel/E7520/northbridge.c	(Revision 2475)
+++ src/northbridge/intel/E7520/northbridge.c	(Arbeitskopie)
@@ -264,7 +264,7 @@
 	}
 }
 
-struct chip_operations northbridge_intel_E7520_ops = {
+struct chip_operations northbridge_intel_e7520_ops = {
 	CHIP_NAME("Intel E7520 Northbridge")
 	.enable_dev = enable_dev,
 };
Index: src/northbridge/intel/E7520/chip.h
===================================================================
--- src/northbridge/intel/E7520/chip.h	(Revision 2475)
+++ src/northbridge/intel/E7520/chip.h	(Arbeitskopie)
@@ -1,7 +1,7 @@
-struct northbridge_intel_E7520_config
+struct northbridge_intel_e7520_config
 {
         /* Interrupt line connect */
         unsigned int intrline;
 };
 
-extern struct chip_operations northbridge_intel_E7520_ops;
+extern struct chip_operations northbridge_intel_e7520_ops;
Index: src/northbridge/intel/E7520/pciexp_porta.c
===================================================================
--- src/northbridge/intel/E7520/pciexp_porta.c	(Revision 2475)
+++ src/northbridge/intel/E7520/pciexp_porta.c	(Arbeitskopie)
@@ -8,7 +8,7 @@
 #include "chip.h"
 #include <part/hard_reset.h>
                                                            
-typedef struct northbridge_intel_E7520_config config_t;
+typedef struct northbridge_intel_e7520_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7525/pciexp_porta1.c
===================================================================
--- src/northbridge/intel/E7525/pciexp_porta1.c	(Revision 2475)
+++ src/northbridge/intel/E7525/pciexp_porta1.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7525/pciexp_portb.c
===================================================================
--- src/northbridge/intel/E7525/pciexp_portb.c	(Revision 2475)
+++ src/northbridge/intel/E7525/pciexp_portb.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7525/pciexp_portc.c
===================================================================
--- src/northbridge/intel/E7525/pciexp_portc.c	(Revision 2475)
+++ src/northbridge/intel/E7525/pciexp_portc.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {
Index: src/northbridge/intel/E7525/northbridge.c
===================================================================
--- src/northbridge/intel/E7525/northbridge.c	(Revision 2475)
+++ src/northbridge/intel/E7525/northbridge.c	(Arbeitskopie)
@@ -264,7 +264,7 @@
 	}
 }
 
-struct chip_operations northbridge_intel_E7525_ops = {
+struct chip_operations northbridge_intel_e7525_ops = {
 	CHIP_NAME("Intel E7525 Northbridge")
 	.enable_dev = enable_dev,
 };
Index: src/northbridge/intel/E7525/chip.h
===================================================================
--- src/northbridge/intel/E7525/chip.h	(Revision 2475)
+++ src/northbridge/intel/E7525/chip.h	(Arbeitskopie)
@@ -1,7 +1,7 @@
-struct northbridge_intel_E7525_config
+struct northbridge_intel_e7525_config
 {
         /* Interrupt line connect */
         unsigned int intrline;
 };
 
-extern struct chip_operations northbridge_intel_E7525_ops;
+extern struct chip_operations northbridge_intel_e7525_ops;
Index: src/northbridge/intel/E7525/pciexp_porta.c
===================================================================
--- src/northbridge/intel/E7525/pciexp_porta.c	(Revision 2475)
+++ src/northbridge/intel/E7525/pciexp_porta.c	(Arbeitskopie)
@@ -7,7 +7,7 @@
 #include <arch/io.h>
 #include "chip.h"
                                                            
-typedef struct northbridge_intel_E7525_config config_t;
+typedef struct northbridge_intel_e7525_config config_t;
 
 static void pcie_init(struct device *dev)
 {
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 189 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20061026/29e0b475/attachment.sig>