[LinuxBIOS] On flashrom architecture

Stefan Reinauer stepan at coresystems.de
Sat Apr 28 22:38:28 CEST 2007


* Darmawan Salihun <darmawan.salihun at gmail.com> [070428 13:44]:
>     Yes. It's a specific sc520 system which has it's flash mapped to another
>     position. I was a bit uncertain whether to allow flash probing in that
>     area on non-TS5300 systems. Do you have a good idea for a runtime check?

In fact, the SC520 has three possible flash banks that should be probed,
instead of the single hard coded one:

Registers are
BOOTCS (MMCR offs 0x50), ROMCS1 (MMCR offs 0x54), ROMCS2 (MMCR offs 0x56)

and one of PAR0-PAR15 (32bit registers at 0x88-0xc4) - The highest 3 bit
describe the target, 100 is BOOTCS, 101 is ROMCS1, 110 is ROMCS2

See Élan™ SC520 Microcontroller Register Set Manual

The Linux MTD mapping driver suggests changing the default mapping of
those areas for some interesting reasons. We might take the chance to
unify the ROM mappings on all SC520 boards.

Ron?

Stefan

-- 
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info at coresystems.dehttp://www.coresystems.de/




More information about the coreboot mailing list