[LinuxBIOS] question about via chipset v-link and ram init

[aaron lwe]

Corey Osgood <corey.osgood at gmail.com> wrote:

> aaron lwe wrote:
> > On Dec 10, 2007 10:19 AM, Corey Osgood <corey.osgood at gmail.com
> > <mailto: corey.osgood at gmail.com>> wrote:
> >
> >     aaron lwe wrote:
> >     > Dear all,
> >     >
> >     > the via v-link bus is for data communication between northbridge
> and
> >     > sourthbridge,
> >     > if I just want to make dram work, do I need to configure the
> >     v-link bus?
> >     >
> >     > thanks.
> >
> >     No, vlink can be handled before or after ram init, and it isn't even
>
> >     necessary, if no config is done it will default to the slowest
> >     operating
> >     mode (newer chipsets may bootstrap to higher modes, depending on
> >     motherboard design). However, you do have to program the CPU bus
> >     registers and all the various dram config registers before ram init.
> >     Getting these settings right may be a real pain, depending on what
> >     chipset you're dealing with.
> >
> >     -Corey
> >
> >
> > Thanks Corey. I've been trying to make cn700 work, until now without
> luck.
> > I've programmed host bus and some dram controller registers, but not
> all.
> > how can I know which registers should be programmed and which needn't?
> > can you give me some advices? thanks.
> >
>
> I'm already nearly done with the cn700, please try the attached patch. I
> apologize if there's any cruft in there, I'm working on another project
> right this moment, so I don't have time for a good cleanup.
>
> -Corey
>

Thanks a lot, after a few times trying, I got a question.
Does the IDE/Sata settings in auto.c has any effect on dram?
If not, I would like first comment those code, 'cause I got an "IDE
Controller not found!"
error once booted and then die, which is wired.
When I comment those code, I can successfully went to sdram configure
functions.
but the ram_check displayed many failures:
LinuxBIOS-2.0.0.0-Normal Sun Dec 16 18:09:41 EST 2007 starting...
Found good data, testing it 01 02 03 04 05 Test passed
Enabling shadow ram
Setting ram bank size to 0x40
RAM Enable 1: Apply NOP
    Sending RAM command 0x11 to 0x00000000
RAM Enable 2: Precharge all
    Sending RAM command 0x12 to 0x00000000
RAM Enable 4: Mode register set
    Sending RAM command 0x13 to 0x00002000
    Sending RAM command 0x13 to 0x00000800
RAM Enable 2: Precharge all
    Sending RAM command 0x12 to 0x00000000
RAM Enable 3: CBR
    Sending RAM command 0x14 to 0x00000000
RAM Enable 4: Mode register set
    Sending RAM command 0x13 to 0x000022d8
RAM Enable 4: Mode register set
    Sending RAM command 0x13 to 0x00021c20
    Sending RAM command 0x13 to 0x00020020
RAM Enable 5: Normal operation
    Sending RAM command 0x10 to 0x00000000
Testing DRAM : 00000000-00000100
DRAM fill: 00000000-00000100
00000000
00000100
DRAM filled
DRAM verify: 00000000-00000100
00000000
Fail: @0x00000000 Read value=0xffffffff
Fail: @0x00000004 Read value=0xffffffff
Fail: @0x00000008 Read value=0xffffffff
Fail: @0x0000000c Read value=0xffffffff
Fail: @0x00000010 Read value=0xff299dfe
Fail: @0x00000014 Read value=0xfbeafd6a
Fail: @0x00000018 Read value=0xff7f98ff
Fail: @0x0000001c Read value=0xfbfff7c5
Fail: @0x00000020 Read value=0xffffffff
Fail: @0x00000024 Read value=0xffffffff
Fail: @0x00000028 Read value=0xffffffff
Fail: @0x0000002c Read value=0xffffffff
Fail: @0x00000030 Read value=0xffffdeff
Fail: @0x00000034 Read value=0xfffbff4a
Fail: @0x00000038 Read value=0xfe00cbef
Fail: @0x0000003c Read value=0xffed7202
Fail: @0x00000040 Read value=0xff7de3ff
Fail: @0x00000044 Read value=0xffffff52
Fail: @0x00000048 Read value=0xd310213f
Fail: @0x0000004c Read value=0xefcf2401
Fail: @0x00000050 Read value=0x2dc055f9
Fail: @0x00000054 Read value=0xbfb7a39e
Fail: @0x00000058 Read value=0xffdf3bff
Fail: @0x0000005c Read value=0xffffdf13
Fail: @0x00000060 Read value=0x860e2865
Fail: @0x00000064 Read value=0xda6f2906
Fail: @0x00000068 Read value=0xff057fff
Fail: @0x0000006c Read value=0xbffb3634
Fail: @0x00000070 Read value=0xffc8fbff
Fail: @0x00000074 Read value=0xfefffe98
... ...
Any ideas? Should I change all the values of the host bus and dram
controller registers
to my board's factory BIOS' values? The size of my dram module is 512MB, one
external bank,
single sided, ddr2-533 device. So I guess maybe the value you set should be
ok with
this dimm?
Thanks.
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