[LinuxBIOS] [PATCH] flashrom: add support for the ST M25P family

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Mon Dec 17 15:53:42 CET 2007


Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets.
Pretty-print the chip status register (including block lock information)
for ST M25P family chips on erase.
Print the chip status register for all SPI chips on erase.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-m25p/flash.h
===================================================================
--- flashrom-m25p/flash.h	(Revision 3009)
+++ flashrom-m25p/flash.h	(Arbeitskopie)
@@ -172,7 +172,15 @@
  * byte of device ID is related to log(bitsize) at least for some chips.
  */
 #define ST_ID			0x20	/* ST */
+#define ST_M25P05A		0x2010
+#define ST_M25P10A		0x2011
+#define ST_M25P20		0x2012
+#define ST_M25P40		0x2013
 #define ST_M25P80		0x2014
+#define ST_M25P16		0x2015
+#define ST_M25P32		0x2016
+#define ST_M25P64		0x2017
+#define ST_M25P128		0x2018
 #define ST_M50FLW040A		0x08
 #define ST_M50FLW040B		0x28
 #define ST_M50FLW080A		0x80
Index: flashrom-m25p/flashchips.c
===================================================================
--- flashrom-m25p/flashchips.c	(Revision 3009)
+++ flashrom-m25p/flashchips.c	(Arbeitskopie)
@@ -140,8 +140,24 @@
 	 probe_jedec,	erase_chip_jedec,	write_jedec},
 	{"M29F040B",	ST_ID, 		ST_M29F040B,	512, 64 * 1024,
 	 probe_29f040b, erase_29f040b,	write_29f040b},
+	{"M25P05-A",	ST_ID,		ST_M25P05A,	64, 32 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P10-A",	ST_ID,		ST_M25P10A,	128, 32 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P20",	ST_ID,		ST_M25P20,	256, 64 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P40",	ST_ID,		ST_M25P40,	512, 64 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
 	{"M25P80",	ST_ID,		ST_M25P80,	1024, 64 * 1024,
 	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P16",	ST_ID,		ST_M25P16,	2048, 64 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P32",	ST_ID,		ST_M25P32,	4096, 64 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P64",	ST_ID,		ST_M25P64,	8192, 64 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
+	{"M25P128",	ST_ID,		ST_M25P128,	16384, 256 * 1024,
+	 probe_spi,	generic_spi_chip_erase_c7,	generic_spi_chip_write},
 	{"82802ab",	137,		173,		512, 64 * 1024,
 	 probe_82802ab, erase_82802ab,	write_82802ab},
 	{"82802ac",	137,		172,		1024, 64 * 1024,
Index: flashrom-m25p/spi.c
===================================================================
--- flashrom-m25p/spi.c	(Revision 3009)
+++ flashrom-m25p/spi.c	(Arbeitskopie)
@@ -277,14 +277,45 @@
 	return readarr[0];
 }
 
+void generic_spi_prettyprint_status_register_st_m25p(uint8_t status)
+{
+	printf("Chip status register: Status Register Write Disable (SRWD) is "
+		"%sset\n", (status & (1 << 7)) ? "" : "not ");
+	printf("Chip status register: Block Protect 2 (BP2) is "
+		"%sset\n", (status & (1 << 4)) ? "" : "not ");
+	printf("Chip status register: Block Protect 1 (BP1) is "
+		"%sset\n", (status & (1 << 3)) ? "" : "not ");
+	printf("Chip status register: Block Protect 0 (BP0) is "
+		"%sset\n", (status & (1 << 2)) ? "" : "not ");
+	printf("Chip status register: Write Enable Latch (WEL) is "
+		"%sset\n", (status & (1 << 1)) ? "" : "not ");
+	printf("Chip status register: Write In Progress (WIP) is "
+		"%sset\n", (status & (1 << 7)) ? "" : "not ");
+}
+
+void generic_spi_prettyprint_status_register(struct flashchip *flash)
+{
+	uint8_t status;
+
+	status = generic_spi_read_status_register();
+	printf("Chip status register is %02x\n", status);
+	switch (flash->manufacture_id) {
+	case ST_ID:
+		if ((flash->model_id & 0xff00) == 0x2000)
+			generic_spi_prettyprint_status_register_st_m25p(status);
+		break;
+	}
+}
+	
 int generic_spi_chip_erase_c7(struct flashchip *flash)
 {
 	const unsigned char cmd[] = JEDEC_CE_C7;
-	uint8_t statusreg;
+	
+	/* Print the status register before erase to tell the user about
+	 * possible write protection.
+	 */
+	generic_spi_prettyprint_status_register(flash);
 
-	statusreg = generic_spi_read_status_register();
-	printf("chip status register before erase is %02x\n", statusreg);
-	
 	generic_spi_write_enable();
 	/* Send CE (Chip Erase) */
 	generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);






More information about the coreboot mailing list