[LinuxBIOS] Question about PCI Config Space byte rd/wr in HT

[Segher Boessenkool]

[Don't reply to an unrelated post, please start a new
thread instead].

> If software tries to do a byte rd/wr access to PCI config access, say 
> in
> linux or BIOS, how would it show up on the HT bus?

As a byte access to config space -- what else?

Read the HT specification (from hypertransport.org)
if you need to know the details.

> I'm assuming that config space access is initiated through the 
> southbridge.

It's done on the CPU chip (it detects accesses to
legacy I/O address 0xfc8/0xcfc).

> Anyone know if an HT device will ever have to expect byte access to its
> config space?

Yes, some people know.  Yes, they have to expect (and
allow) byte accesses.


Segher