[LinuxBIOS] Question about PCI Config Space byte rd/wr in HT

[Perry Wang]

Thanks for the clarification.

The reason I had some doubts is that there are devices out there that don't
support byte access in config space (at least one HT IP vendor doesn't seem
to support it) and I've been wondering how people have been able to go get
away with this.

I just read the PCI spec and it says that the address during config cycles
is dword address, but I also saw some byte enable signals so it looks like
it's definitely possible to issue byte access to config space in the PCI
world.  

Regards,
Perry

> -----Original Message-----
> From: Segher Boessenkool [mailto:segher at kernel.crashing.org]
> Sent: Tuesday, February 13, 2007 12:20 PM
> To: Perry Wang
> Cc: linuxbios at linuxbios.org
> Subject: Re: [LinuxBIOS] Question about PCI Config Space byte rd/wr in HT
> 
> [Don't reply to an unrelated post, please start a new
> thread instead].
> 
> > If software tries to do a byte rd/wr access to PCI config access, say
> > in
> > linux or BIOS, how would it show up on the HT bus?
> 
> As a byte access to config space -- what else?
> 
> Read the HT specification (from hypertransport.org)
> if you need to know the details.
> 
> > I'm assuming that config space access is initiated through the
> > southbridge.
> 
> It's done on the CPU chip (it detects accesses to
> legacy I/O address 0xfc8/0xcfc).
> 
> > Anyone know if an HT device will ever have to expect byte access to its
> > config space?
> 
> Yes, some people know.  Yes, they have to expect (and
> allow) byte accesses.
> 
> 
> Segher