[LinuxBIOS] #87: flashrom issues on m57sli-s4

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Thu Nov 8 16:51:33 CET 2007


Hi Ward,

On 08.11.2007 16:22, Ward Vandewege wrote:
> On Thu, Nov 08, 2007 at 02:05:16PM -0000, LinuxBIOS wrote:
>   
>> #87: flashrom issues on m57sli-s4
>>
>>  I need superiotool output for a board with parallel flash running under
>>  LB. NOW.
>>     
>
> LinuxBIOS:          http://ward.vandewege.net/superiotool-lb.m57sli.dump
> Proprietary BIOS:   http://ward.vandewege.net/superiotool-prop.m57sli.dump
>   

Thanks!

ldn any
idx 07 20 21 22 23 24 2b 
val 06 87 16 00 01 00 00 plcc lb
                xx
val 0a 87 16 00 11 00 00 plcc prop
                   xx
val 0a 87 16 00 11 1a 00 soic prop
                xx xx
def NA 87 16 01 00 00 00
 
ldn 0x7 
idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd
val 00 00 00 00 00 00 1f 00 00 00 00 00 00 00 01 20 38 00 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 00 plcc lb
       xx xx    xx             xx                xx                         xx          xx       xx xx          xx                         xx                xx
val 00 43 20 00 81 00 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 plcc prop
                                     xx xx    xx
val 00 43 20 00 81 00 1f 00 00 08 00 08 20 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 43 20 00 00 00 40 00 00 00 00 00 00 00 00 10 40 00 00 00 00 28 00 00 00 00 00 32 00 soic prop
    xx xx xx xx xx    xx       xx    xx xx       xx                                     xx    xx xx xx xx    xx xx    xx                   xx xx             xx
def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 

The patch below will NOT work, I have yet to figure out how to tell
Config.lb that I want to set a 8-bit value (which is a simple value
and not irq/drq/io) in a superio section. But it should be enough to
base a real patch on it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	(Revision 2953)
+++ LinuxBIOSv2/src/mainboard/gigabyte/m57sli/Config.lb	(Arbeitskopie)
@@ -239,7 +239,9 @@
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
 						chip superio/ite/it8716f
-							device pnp 2e.0 off #  Floppy
+							device pnp 2e.0 off #  Floppy and anyLDN
+								0x23 = 0x11 # watchdog from CLKIN, CLKIN = 24 MHz
+								#0x24 = 0x1a # serial flash (SPI only)
                 	                 			io 0x60 = 0x3f0
                 	                			irq 0x70 = 6
                 	                			drq 0x74 = 2
@@ -269,6 +271,30 @@
                 	        			device pnp 2e.6 on #  Mouse
                 	                			irq 0x70 = 12
 							end
+                	        			device pnp 2e.7 on #  GPIO, SPI flash
+								0x25 = 0x0 # pin 84 is not GP10
+								0x26 = 0x43 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+								0x27 = 0x20 # pin 13 is GP35
+								#0x28 = 0x0 # pin 70 is not GP46
+								0x29 = 0x81 # pin 6,3,128,127,126 is GP63,64,65,66,67
+								#0x2c = 0x1f # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+								io 0x62 = 0x800 # simple i/o base
+                	                			#io 0x64 = 0x820 # serial flash io (SPI only)
+								#0x71 = 0x1 # watch dog force timeout (parallel flash only)
+								irq 0x72 = 0x0 # no WDT interrupt
+								0xb8 = 0x0 # GPIO pin set 1 disable internal pullup
+								0xbc = 0x01 # GPIO pin set 5 enable internal pullup
+								#0xc0 = 0x0 # SIO pin set 1 alternate function
+								0xc1 = 0x43 # SIO pin set 2 mixed function
+								0xc2 = 0x20 # SIO pin set 3 mixed function
+								#0xc3 = 0x0 # SIO pin set 4 alternate function
+								#0xc8 = 0x0 # SIO pin set 1 input mode
+								0xc9 = 0x0 # SIO pin set 2 mixed input/output mode
+								#0xcb = 0x0 # SIO pin set 4 input mode
+								#0xf0 = 0x10 # generate SMI# on EC IRQ
+								#0xf1 = 0x40 # SMI# level trigger
+								0xf6 = 0x28 # HWMON alert beep pin location
+							end
                 	        			device pnp 2e.8 off #  MIDI
 								io 0x60 = 0x300
 								irq 0x70 = 10
@@ -305,6 +331,7 @@
                                                         device i2c 57 on end
                                                 end 
 					end # SM
+#wtf?!? we already have device pci 1.1 in the section above
                                         device pci 1.1 on # SM 1
 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 #                                                chip drivers/generic/generic #PCIXA Slot1


The "wtf?!?" comment is intentional and designates another bug. However,
I have no idea which device number we need here.

Regards,
Carl-Daniel





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