[LinuxBIOS] Setup of Memory Controller

[Nate]

>That depends on whether the DRC is seen as a coherent device or a non-coherent one. In the first case you would map it as DRAM (toward a node id), in the second as MMIO (toward a node:link).
 
 As it is in the Tyan motherboard now, the FPGA is seen as a non-coherent HT cave device.
 
 >I'm not familiar with the DRC -- what kind of PCI Id is it assigned to?
 
 The "supported" intent of the DRC system is to use the FPGA as an application accelerator. Lspci output looks like this:
 
 0000:40:01.0 Co-processor: DRC Computer Corp.: Unknown device 4200 (rev a1)
 0000:40:01.1 Co-processor: DRC Computer Corp.: Unknown device 4201
 0000:40:01.2 Co-processor: DRC Computer Corp.: Unknown device 4202
 0000:40:01.3 Co-processor: DRC Computer Corp.: Unknown device 4203
 
 iomem:
 
 fc400000-fc41ffff : 0000:40:01.0
 fcc0000000-fcdfffffff : 0000:40:01.0
 
 >I'm not sure you can bypass the Opteron memory controller (in terms of cache controller etc) completely, but not using the Opteron-connected DRAM at all shouldn't be too hard. Not sure how it would react to having all of its memory mapped as MMIO, though...
 
 Hmm... Your right. I dont want to use the Opteron connected DRAM and Im not looking to replace all of northbridge. I had thought about mapping all addresses to memory-mapped IO of the FPGA as the AMD docs say that "An address that maps to both DRAM and memory-mapped I/O will be routed to MMIO".  An avenue definitely worth testing. However I would rather the system see my memory controller as the gate to the sytems DRAM. 
 
 Im currently looking at the resourcemap.c for the tyan s2891 and looking at simply changing the hex value for the DRAM Limit and Base address for offset 44 and 40 to point to node 1 rather than node 0 and cross my fingers. Im also trying to figure out why some of the registers are commented out. Any ideas? It would leave me to believe these registers are setup by the kernel later on...
 
 I should receive my biossavior tomorrow and commence testing over the break.
 
 nate

Arne Georg Gleditsch <argggh at dolphinics.no> wrote: Linux Bios 
 writes:
> Thanks Ron, I'm from the Air Force Institute of Technology in Ohio. I admit I
> am very simple minded. I am unable to see where I would change the routing in
> early setup. So far I have found myself in
>
> src >> northbridge >> amd >> amdk8 >> raminit.c
>
> This appears to be where northbridge is setup and where I would route memory
> requests to my memory conrtoller. However it looks to be coded by node_id. My
> FPGA would not be recognized necessarily as a node because its not an opteron.
> right?

That depends on whether the DRC is seen as a coherent device or a
non-coherent one.  In the first case you would map it as DRAM (toward
a node id), in the second as MMIO (toward a node:link).  I'm not
familiar with the DRC -- what kind of PCI Id is it assigned to?  I'm
not sure you can bypass the Opteron memory controller (in terms of
cache controller etc) completely, but not using the Opteron-connected
DRAM at all shouldn't be too hard.  Not sure how it would react to
having all of its memory mapped as MMIO, though...

-- 
        Arne.

-- 
linuxbios mailing list
linuxbios at linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios


       
---------------------------------
Be a better sports nut! Let your teams follow you with Yahoo Mobile. Try it now.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20071120/3aa66fe8/attachment.html>