[LinuxBIOS] [PATCH] add support the IEI PCISA-LX
Nikolay Petukhov
nikolaypetukhov at gmail.com
Fri Nov 30 13:03:44 CET 2007
Here is second edition of patch.
But it required pirq.patch from
http://www.linuxbios.org/pipermail/linuxbios/2007-November/027358.html
to support IRQ routing.
2007/11/27, Uwe Hermann <uwe at hermann-uwe.de>:
> On Mon, Nov 26, 2007 at 12:25:45PM +0500, Nikolay Petukhov wrote:
> > This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)
> > is based on amd-lx800/cs5536, so most of the on-board hardware is work
> > normally.
>
> Thanks a lot! Here's a quick review:
>
> I think the full name for this specific board is "PCISA-LX-R11",
> correct? If so, please use that everywhere (directory names, strings,
> variable names, comments). "PCISA-LX" seems to be the general name for a
> whole family of boards.
>
> So the directory name should probably be 'pcisa-lx-r11'.
>
On page http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX ,
this board has Part No. PCISA-LX-800-R10.
So directory name should be pcisa-lx-800-r10.
>
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/cache_as_ram_auto.c LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/cache_as_ram_auto.c
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/cache_as_ram_auto.c 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/cache_as_ram_auto.c 2007-11-26 09:50:43.000000000 +0500
> > @@ -0,0 +1,138 @@
> > +/*
> > + * This file is part of the LinuxBIOS project.
> > + *
> > + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
>
>
> > + * Borrowed from amd/db800.
>
> Either the code you grabbed from the DB800 target is trivial (then drop
> this line completely), or it is not (then retain the Copyright lines from
> the respective DB800 file please).
>
> In this case the file is a plain copy of the DB800 one, with small fixes
> in the #defines at the beginning, so please keep the original
> copyright/license header and drop the "Borrowed from amd/db800".
>
Copyright retained from amd/db800.
>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +#define ASSEMBLY 1
> > +
> > +#include <stdint.h>
> > +#include <device/pci_def.h>
> > +#include <arch/io.h>
> > +#include <device/pnp_def.h>
> > +#include <arch/hlt.h>
> > +#include "pc80/serial.c"
> > +#include "arch/i386/lib/console.c"
> > +#include "ram/ramtest.c"
> > +#include "cpu/x86/bist.h"
> > +#include "cpu/x86/msr.h"
> > +#include <cpu/amd/lxdef.h>
> > +#include <cpu/amd/geode_post_code.h>
> > +#include "southbridge/amd/cs5536/cs5536.h"
> > +
> > +#define POST_CODE(x) outb(x, 0x80)
> > +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> > +
> > +#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
> > +#include "southbridge/amd/cs5536/cs5536_early_setup.c"
> > +#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
> > +
> > +static inline int spd_read_byte(unsigned int device, unsigned int address)
> > +{
> > + return smbus_read_byte(device, address);
> > +}
> > +
> > +#define ManualConf 1 /* Do automatic strapped PLL config */
> > +#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
> > +#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
> > +#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
> > +//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
> > +/* Hold Count - how long we will sit in reset */
> > +#define PLLMSRlo 0x00DE6000
> > +
> > +#define DIMM0 0xA0
> > +#define DIMM1 0xA2
> > +#include "northbridge/amd/lx/raminit.h"
> > +#include "northbridge/amd/lx/pll_reset.c"
> > +#include "northbridge/amd/lx/raminit.c"
> > +#include "sdram/generic_sdram.c"
> > +#include "cpu/amd/model_lx/cpureginit.c"
> > +#include "cpu/amd/model_lx/syspreinit.c"
> > +
> > +static void msr_init(void)
> > +{
> > + msr_t msr;
> > +
> > + /* Setup access to the cache for under 1MB. */
> > + msr.hi = 0x24fffc02;
> > + msr.lo = 0x1000A000; /* 0-A0000 write back */
> > + wrmsr(CPU_RCONF_DEFAULT, msr);
> > +
> > + msr.hi = 0x0; /* Write back */
> > + msr.lo = 0x0;
> > + wrmsr(CPU_RCONF_A0_BF, msr);
> > + wrmsr(CPU_RCONF_C0_DF, msr);
> > + wrmsr(CPU_RCONF_E0_FF, msr);
> > +
> > + /* Setup access to the cache for under 640K. Note MC not setup yet. */
> > + msr.hi = 0x20000000;
> > + msr.lo = 0xfff80;
> > + wrmsr(MSR_GLIU0 + 0x20, msr);
> > +
> > + msr.hi = 0x20000000;
> > + msr.lo = 0x80fffe0;
> > + wrmsr(MSR_GLIU0 + 0x21, msr);
> > +
> > + msr.hi = 0x20000000;
> > + msr.lo = 0xfff80;
> > + wrmsr(MSR_GLIU1 + 0x20, msr);
> > +
> > + msr.hi = 0x20000000;
> > + msr.lo = 0x80fffe0;
> > + wrmsr(MSR_GLIU1 + 0x21, msr);
> > +}
>
> As this function is exactly the same for this board (and DB800), is it
> possible that it's not really board-specific anyway? If so, it should
> be moved to a global location in the chipset code.
>
>
> > +
> > +static void mb_gpio_init(void)
> > +{
> > + /* Early mainboard specific GPIO setup. */
> > +}
> > +
> > +void cache_as_ram_main(void)
> > +{
> > + POST_CODE(0x01);
> > +
> > + static const struct mem_controller memctrl[] = {
> > + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
>
> I think you can/should just use DIMM0 / DIMM1 here.
>
I am not sure.
>
> > + };
> > +
> > + SystemPreInit();
> > + msr_init();
> > +
> > + cs5536_early_setup();
> > +
> > + /* Note: must do this AFTER the early_setup! It is counting on some
> > + * early MSR setup for CS5536.
> > + */
> > + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
> > + mb_gpio_init();
> > + uart_init();
> > + console_init();
> > +
> > + pll_reset(ManualConf);
> > +
> > + cpuRegInit();
> > +
> > + sdram_initialize(1, memctrl);
> > +
> > + /* Check memory. */
> > + /* ram_check(0x00000000, 640 * 1024); */
> > +
> > + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
> > + return;
> > +}
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/chip.h LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/chip.h
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/chip.h 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/chip.h 2007-11-26 09:50:43.000000000 +0500
> > @@ -0,0 +1,25 @@
> > +/*
> > + * This file is part of the LinuxBIOS project.
> > + *
> > + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +extern struct chip_operations mainboard_iei_pcisa_lx_ops;
> > +
> > +struct mainboard_iei_pcisa_lx_config {
> > + int nothing;
> > +};
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/cmos.layout LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/cmos.layout
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/cmos.layout 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/cmos.layout 2007-11-26 09:50:43.000000000 +0500
>
> You have
>
> default HAVE_OPTION_TABLE = 0
> default USE_OPTION_TABLE = 0
>
> in Options.lb so this file is never used and we should drop it (or
> enable it's usage, if it's tested and works).
>
> Also, it should have a license header.
>
I corrected it.
>
> > @@ -0,0 +1,74 @@
> > +entries
> > +
> > +#start-bit length config config-ID name
> > +#0 8 r 0 seconds
> > +#8 8 r 0 alarm_seconds
> > +#16 8 r 0 minutes
> > +#24 8 r 0 alarm_minutes
> > +#32 8 r 0 hours
> > +#40 8 r 0 alarm_hours
> > +#48 8 r 0 day_of_week
> > +#56 8 r 0 day_of_month
> > +#64 8 r 0 month
> > +#72 8 r 0 year
> > +#80 4 r 0 rate_select
> > +#84 3 r 0 REF_Clock
> > +#87 1 r 0 UIP
> > +#88 1 r 0 auto_switch_DST
> > +#89 1 r 0 24_hour_mode
> > +#90 1 r 0 binary_values_enable
> > +#91 1 r 0 square-wave_out_enable
> > +#92 1 r 0 update_finished_enable
> > +#93 1 r 0 alarm_interrupt_enable
> > +#94 1 r 0 periodic_interrupt_enable
> > +#95 1 r 0 disable_clock_updates
> > +#96 288 r 0 temporary_filler
> > +0 384 r 0 reserved_memory
> > +384 1 e 4 boot_option
> > +385 1 e 4 last_boot
> > +386 1 e 1 ECC_memory
> > +388 4 r 0 reboot_bits
> > +392 3 e 5 baud_rate
> > +400 1 e 1 power_on_after_fail
> > +412 4 e 6 debug_level
> > +416 4 e 7 boot_first
> > +420 4 e 7 boot_second
> > +424 4 e 7 boot_third
> > +428 4 h 0 boot_index
> > +432 8 h 0 boot_countdown
> > +1008 16 h 0 check_sum
> > +
> > +enumerations
> > +
> > +#ID value text
> > +1 0 Disable
> > +1 1 Enable
> > +2 0 Enable
> > +2 1 Disable
> > +4 0 Fallback
> > +4 1 Normal
> > +5 0 115200
> > +5 1 57600
> > +5 2 38400
> > +5 3 19200
> > +5 4 9600
> > +5 5 4800
> > +5 6 2400
> > +5 7 1200
> > +6 6 Notice
> > +6 7 Info
> > +6 8 Debug
> > +6 9 Spew
> > +7 0 Network
> > +7 1 HDD
> > +7 2 Floppy
> > +7 8 Fallback_Network
> > +7 9 Fallback_HDD
> > +7 10 Fallback_Floppy
> > +#7 3 ROM
> > +
> > +checksums
> > +
> > +checksum 392 1007 1008
> > +
> > +
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/Config.lb LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/Config.lb
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/Config.lb 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/Config.lb 2007-11-26 09:50:43.000000000 +0500
>
> Add a license header, please.
>
>
> > @@ -0,0 +1,194 @@
> > +##
> > +## Compute the location and size of where this firmware image
> > +## (linuxBIOS plus bootloader) will live in the boot rom chip.
> > +##
> > +if USE_FALLBACK_IMAGE
> > + default ROM_SECTION_SIZE = FALLBACK_SIZE
> > + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
> > +else
> > + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
> > + default ROM_SECTION_OFFSET = 0
> > +end
> > +
> > +##
> > +## Compute the start location and size size of
> > +## The linuxBIOS bootloader.
> > +##
> > +
> > +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
> > +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
> > +
> > +##
> > +## Compute where this copy of linuxBIOS will start in the boot rom
> > +##
> > +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
> > +
> > +##
> > +## Compute a range of ROM that can cached to speed up linuxBIOS,
> > +## execution speed.
> > +##
> > +## XIP_ROM_SIZE must be a power of 2.
> > +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
> > +##
> > +default XIP_ROM_SIZE=65536
> > +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
> > +
> > +
> > +##
> > +## Set all of the defaults for an x86 architecture
> > +##
> > +
> > +arch i386 end
> > +
> > +##
> > +## Build the objects we have code for in this directory.
> > +##
> > +
> > +driver mainboard.o
> > +
> > +if HAVE_PIRQ_TABLE
> > + object irq_tables.o
> > +end
> > +
> > +if USE_DCACHE_RAM
> > + #compile cache_as_ram.c to auto.inc
> > + makerule ./cache_as_ram_auto.inc
> > + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
> > + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
> > + action "perl -e 's/.rodata/.rom.data/g' -pi $@"
> > + action "perl -e 's/.text/.section .rom.text/g' -pi $@"
> > + end
> > +end
> > +
> > +
> > +##
> > +## Build our 16 bit and 32 bit linuxBIOS entry code
> > +##
> > +mainboardinit cpu/x86/16bit/entry16.inc
> > +mainboardinit cpu/x86/32bit/entry32.inc
> > +ldscript /cpu/x86/16bit/entry16.lds
> > +ldscript /cpu/x86/32bit/entry32.lds
> > +
> > +##
> > +## Build our reset vector (This is where linuxBIOS is entered)
> > +##
> > +if USE_FALLBACK_IMAGE
> > + mainboardinit cpu/x86/16bit/reset16.inc
> > + ldscript /cpu/x86/16bit/reset16.lds
> > +else
> > + mainboardinit cpu/x86/32bit/reset32.inc
> > + ldscript /cpu/x86/32bit/reset32.lds
> > +end
> > +
> > +### Should this be in the northbridge code?
> > +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
> > +
> > +##
> > +## Include an id string (For safe flashing)
> > +##
> > +mainboardinit arch/i386/lib/id.inc
> > +ldscript /arch/i386/lib/id.lds
> > +
> > +###
> > +### This is the early phase of linuxBIOS startup
> > +### Things are delicate and we test to see if we should
> > +### failover to another image.
> > +###
> > +if USE_FALLBACK_IMAGE
> > + ldscript /arch/i386/lib/failover.lds
> > +# mainboardinit ./failover.inc
> > +end
> > +
> > +###
> > +### O.k. We aren't just an intermediary anymore!
> > +###
> > +
> > +##
> > +## Setup RAM
> > +##
> > +mainboardinit cpu/x86/fpu/enable_fpu.inc
> > +
> > +if USE_DCACHE_RAM
> > + mainboardinit cpu/amd/model_lx/cache_as_ram.inc
> > + mainboardinit ./cache_as_ram_auto.inc
> > +end
> > +
> > +##
> > +## Include the secondary Configuration files
> > +##
> > +dir /pc80
> > +config chip.h
> > +
> > +chip northbridge/amd/lx
> > + device pci_domain 0 on
> > + device pci 1.0 on end # Northbridge
> > + device pci 1.1 on end # Graphics
> > + chip southbridge/amd/cs5536
> > + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
> > + # SIRQ Mode = Active(Quiet) mode. Save power....
> > + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
> > + register "lpc_serirq_enable" = "0x000010da"
> > + register "lpc_serirq_polarity" = "0x0000EF25"
> > + register "lpc_serirq_mode" = "1"
> > + register "enable_gpio_int_route" = "0x0D0C0700"
> > + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
> > + register "enable_USBP4_device" = "1" # 0: host, 1:device
> > + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
> > + register "com1_enable" = "0"
> > + register "com1_address" = "0x3F8"
> > + register "com1_irq" = "4"
> > + register "com2_enable" = "0"
> > + register "com2_address" = "0x2F8"
> > + register "com2_irq" = "3"
> > + register "unwanted_vpci[0]" = "0" # End of list has a zero
> > + device pci 9.0 on end # Slot1
> > + device pci a.0 on end # Slot2
> > + device pci b.0 on end # Slot3
> > + device pci c.0 on end # Slot4
> > + device pci e.0 on end # Ethernet 0
> > + device pci 10.0 on end # Ethernet 1
> > + device pci 11.0 on end # SATA
> > + device pci f.0 on # ISA Bridge
> > + chip superio/winbond/w83627hf
> > + device pnp 2e.0 off # Floppy
> > + io 0x60 = 0x3f0
> > + irq 0x70 = 6
> > + drq 0x74 = 2
> > + end
> > + device pnp 2e.1 off # Parallel port
> > + io 0x60 = 0x378
> > + irq 0x70 = 7
> > + end
> > + device pnp 2e.2 on # Com1
> > + io 0x60 = 0x3f8
> > + irq 0x70 = 4
> > + end
> > + device pnp 2e.3 off end # Com2
> > + device pnp 2e.5 on # Keyboard
> > + io 0x60 = 0x60
> > + io 0x62 = 0x64
> > + irq 0x70 = 1
> > + irq 0x72 = 12
> > + end
> > + device pnp 2e.6 off end # CIR
> > + device pnp 2e.7 off end # GAME_MIDI_GIPO1
> > + device pnp 2e.8 off end # GPIO2
> > + device pnp 2e.9 off end # GPIO3
> > + device pnp 2e.a off end # ACPI
> > + device pnp 2e.b off end # HW Monitor
> > + end
> > + end
> > + device pci f.2 on end # IDE Controller
> > + device pci f.3 on end # Audio
> > + device pci f.4 on end # OHCI
> > + device pci f.5 on end # EHCI
> > + end
> > + end
> > + # APIC cluster is late CPU init.
> > + device apic_cluster 0 on
> > + chip cpu/amd/model_lx
> > + device apic 0 on end
> > + end
> > + end
> > +end
> > +
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/failover.c LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/failover.c
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/failover.c 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/failover.c 2007-11-26 09:50:43.000000000 +0500
> > @@ -0,0 +1,32 @@
> > +/*
> > + * This file is part of the LinuxBIOS project.
> > + *
> > + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +#define ASSEMBLY 1
> > +
> > +#include <stdint.h>
> > +#include <device/pci_def.h>
> > +#include <device/pci_ids.h>
> > +#include <arch/io.h>
> > +#include "pc80/mc146818rtc_early.c"
> > +
> > +static unsigned long main(unsigned long bist)
> > +{
> > + return bist;
> > +}
>
> Hm, does this mean it's not used at all? If so, drop the file
> completely. You'll have to fix up the Config.lb file a bit so
> it still compiles if you do that (grep for "failover").
>
I corrected it.
>
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/irq_tables.c LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/irq_tables.c
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/irq_tables.c 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/irq_tables.c 2007-11-26 10:02:48.000000000 +0500
> > @@ -0,0 +1,298 @@
> > +/*
> > + * This file is part of the LinuxBIOS project.
> > + *
> > + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
>
>
> > + * Borrowed from amd/db800.
>
> Nope, this one is actually quite different from the DB800 file and
> produced by you manually, I assume? If so, drop the "Borrowed from
> amd/db800".
>
>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +#include <arch/pirq_routing.h>
> > +#include <console/console.h>
> > +#include <arch/io.h>
> > +#include <arch/pirq_routing.h>
>
> arch/pirq_routing.h is only needed once, I think.
>
I drop it.
>
> > +
> > +/* Platform IRQs */
> > +#define PIRQA 11
> > +#define PIRQB 10
> > +#define PIRQC 11
> > +#define PIRQD 5
> > +
> > +/* Link */
> > +#define LINK_PIRQA 1
> > +#define LINK_PIRQB 2
> > +#define LINK_PIRQC 3
> > +#define LINK_PIRQD 4
> > +#define LINK_NONE 0
> > +
> > +/* Map */
> > +#define IRQ_BITMAP_LINKA (1 << PIRQA)
> > +#define IRQ_BITMAP_LINKB (1 << PIRQB)
> > +#define IRQ_BITMAP_LINKC (1 << PIRQC)
> > +#define IRQ_BITMAP_LINKD (1 << PIRQD)
> > +#define IRQ_BITMAP_NOLINK 0x0
> > +
> > +#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD)
> > +
> > +const struct irq_routing_table intel_irq_routing_table = {
> > + PIRQ_SIGNATURE, /* u32 signature */
> > + PIRQ_VERSION, /* u16 version */
> > + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
> > + 0x00, /* Where the interrupt router lies (bus) */
> > + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
> > + EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */
> > + 0x1078, /* Vendor */
> > + 0x0002, /* Device */
> > + 0, /* Crap (miniport) */
> > + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
> > + 0x62, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
> > +
> > + .slots = {
> > + [0] = {
> > + .slot = 0x0, /* means also "on board" */
> > + .bus = 0x00,
> > + .devfn = (0x01<<3)|0x0, /* 0x01 is CS5536 */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + }
> > + }
> > + },
> > +
> > + [1] = {
> > + .slot = 0x0, /* means also "on board" */
> > + .bus = 0x00,
> > + .devfn = (0x0f<<3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_PIRQB, /* Audio */
> > + .bitmap = IRQ_BITMAP_LINKB
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_PIRQD, /* USB */
> > + .bitmap = IRQ_BITMAP_LINKD
> > + }
> > + }
> > + },
> > +
> > + [2] = {
> > + .slot = 0x0, /* means also "on board" */
> > + .bus = 0x00,
> > + .devfn = (0x0e<<3)|0x0, /* 0x0e is eth0 */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQD,
> > + .bitmap = IRQ_BITMAP_LINKD
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + }
> > + }
> > + },
> > +
> > + [3] = {
> > + .slot = 0x0, /* means also "on board" */
> > + .bus = 0x00,
> > + .devfn = (0x10<<3)|0x0, /* 0x10 is eth1 */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQB,
> > + .bitmap = IRQ_BITMAP_LINKB
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + }
> > + }
> > + },
> > +
> > + [4] = {
> > + .slot = 0x0, /* means also "on board" */
> > + .bus = 0x00,
> > + .devfn = (0x11<<3)|0x0, /* 0x11 is SATA */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_NONE,
> > + .bitmap = IRQ_BITMAP_NOLINK
> > + }
> > + }
> > + },
> > +
> > +/*
> > + * ################### backplane ###################
> > + */
> > +
> > +/*
> > + * Not exist on IP-6S, but it PCI1 on IP-7S.
> > + */
>
> ?
>
> Are you trying to make this table compatible with two different boards?
> If yes, does the rest of the code work fine with both of them?
>
Yes, RIR table formed to correct work the PCISA-LX with various backplanes.
>
> > + [5] = {
> > + .slot = 0x1, /* This is real PCI slot. */
> > + .bus = 0x00,
> > + .devfn = (0x09<<3)|0x0, /* 0x09 is PCI1 */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_PIRQB,
> > + .bitmap = IRQ_BITMAP_LINKB
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_PIRQC,
> > + .bitmap = IRQ_BITMAP_LINKC
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_PIRQD,
> > + .bitmap = IRQ_BITMAP_LINKD
> > + }
> > + }
> > + },
> > +/*
> > + * PCI2 IP-6S
> > + */
> > + [6] = {
> > + .slot = 0x2, /* This is real PCI slot. */
> > + .bus = 0x00,
> > + .devfn = (0x0a<<3)|0x0, /* 0x0a is PCI2 on IP-6S */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQD,
> > + .bitmap = IRQ_BITMAP_LINKD
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_PIRQB,
> > + .bitmap = IRQ_BITMAP_LINKB
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_PIRQC,
> > + .bitmap = IRQ_BITMAP_LINKC
> > + }
> > + }
> > + },
> > +/*
> > + * PCI3 IP-6S
> > + */
> > + [7] = {
> > + .slot = 0x3, /* This is real PCI slot. */
> > + .bus = 0x00,
> > + .devfn = (0x0b<<3)|0x0, /* 0x0b is PCI3 on IP-6S */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQC,
> > + .bitmap = IRQ_BITMAP_LINKC
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_PIRQD,
> > + .bitmap = IRQ_BITMAP_LINKD
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_PIRQB,
> > + .bitmap = IRQ_BITMAP_LINKB
> > + }
> > + }
> > + },
> > +/*
> > + * PCI4 IP-6S
> > + */
> > + [8] = {
> > + .slot = 0x4, /* This is real PCI slot. */
> > + .bus = 0x00,
> > + .devfn = (0x0c<<3)|0x0, /* 0x0c is PCI4 on IP-6S */
> > + .irq = {
> > + [0] = { /* <-- 0 means this is INTA# output from the device or slot */
> > + .link = LINK_PIRQB,
> > + .bitmap = IRQ_BITMAP_LINKB
> > + },
> > + [1] = { /* <-- 1 means this is INTB# output from the device or slot */
> > + .link = LINK_PIRQC,
> > + .bitmap = IRQ_BITMAP_LINKC
> > + },
> > + [2] = { /* <-- 2 means this is INTC# output from the device or slot */
> > + .link = LINK_PIRQD,
> > + .bitmap = IRQ_BITMAP_LINKD
> > + },
> > + [3] = { /* <-- 3 means this is INTD# output from the device or slot */
> > + .link = LINK_PIRQA,
> > + .bitmap = IRQ_BITMAP_LINKA
> > + }
> > + }
> > + },
> > + }
> > +};
> > +
> > +unsigned long write_pirq_routing_table(unsigned long addr)
> > +{
> > + /* Put the PIR table in memory and checksum. */
> > + return copy_pirq_routing_table(addr);
> > +}
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/mainboard.c LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/mainboard.c
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/mainboard.c 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/mainboard.c 2007-11-26 09:50:43.000000000 +0500
> > @@ -0,0 +1,195 @@
> > +/*
> > + * This file is part of the LinuxBIOS project.
> > + *
> > + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
> > + * Borrowed from amd/db800.
>
> This file is a plain copy of the DB800 file (+/- variable renames), and
> it's a non-trivial amount of code IMHO, so please keep the original
> copyright/license header.
>
Copyright retained from amd/db800.
>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +#include <console/console.h>
> > +#include <device/device.h>
> > +#include <arch/io.h>
> > +#include <cpu/x86/msr.h>
> > +#include <cpu/amd/lxdef.h>
> > +#include <device/pci_def.h>
> > +#include "../../../southbridge/amd/cs5536/cs5536.h"
> > +#include "chip.h"
> > +
> > +/* Print the platform configuration - do before PCI init or it will not
> > + * work right.
> > + */
> > +void print_conf(void)
> > +{
> > +#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
> > + int i;
> > + unsigned long iol;
> > + msr_t msr;
> > +
> > + int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
> > + CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
> > + CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
> > + GLCP_DELAY_CONTROLS, GL_END
> > + };
> > +
> > + int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
> > + MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
> > + GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
> > + GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
> > + MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
> > + GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
> > + GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
> > + GLIU0_GLD_MSR_COH, GL_END
> > + };
> > +
> > + int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
> > + MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
> > + MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
> > + MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
> > + GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
> > + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
> > + GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
> > + GLIU1_GLD_MSR_COH, GL_END
> > + };
> > +
> > + int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
> > + CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
> > + };
> > +
> > + int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
> > + MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
> > + MDD_IRQM_PRIM, GL_END
> > + };
> > +
> > + int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
> > + GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
> > + GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
> > + };
> > +
> > + int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
> > + MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
> > + MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
> > + };
> > +
> > + printk_debug("---------- CPU ------------\n");
> > +
> > + for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
> > + msr = rdmsr(cpu_msr_defs[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
> > + cpu_msr_defs[i], msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- GLIU 0 ------------\n");
> > +
> > + for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
> > + msr = rdmsr(gliu0_msr_defs[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
> > + gliu0_msr_defs[i], msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- GLIU 1 ------------\n");
> > +
> > + for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
> > + msr = rdmsr(gliu1_msr_defs[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
> > + gliu1_msr_defs[i], msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- RCONF ------------\n");
> > +
> > + for (i = 0; rconf_msr[i] != GL_END; i++) {
> > + msr = rdmsr(rconf_msr[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
> > + msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- VARIA ------------\n");
> > + msr = rdmsr(0x51300010);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
> > + msr.lo);
> > +
> > + msr = rdmsr(0x51400015);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
> > + msr.lo);
> > +
> > + printk_debug("---------- DIVIL IRQ ------------\n");
> > + msr = rdmsr(MDD_IRQM_YLOW);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
> > + msr.lo);
> > + msr = rdmsr(MDD_IRQM_YHIGH);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
> > + msr.hi, msr.lo);
> > + msr = rdmsr(MDD_IRQM_ZLOW);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
> > + msr.lo);
> > + msr = rdmsr(MDD_IRQM_ZHIGH);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
> > + msr.hi, msr.lo);
> > +
> > + printk_debug("---------- PCI ------------\n");
> > +
> > + for (i = 0; pci_msr[i] != GL_END; i++) {
> > + msr = rdmsr(pci_msr[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
> > + msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- LPC/UART DMA ------------\n");
> > +
> > + for (i = 0; dma_msr[i] != GL_END; i++) {
> > + msr = rdmsr(dma_msr[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
> > + msr.hi, msr.lo);
> > + }
> > +
> > + printk_debug("---------- CS5536 ------------\n");
> > +
> > + for (i = 0; cs5536_msr[i] != GL_END; i++) {
> > + msr = rdmsr(cs5536_msr[i]);
> > + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
> > + msr.hi, msr.lo);
> > + }
> > +
> > + iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
> > + printk_debug("IOR 0x%08X is now 0x%08X\n",
> > + GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
> > + iol = inl(GPIOL_EVENTS_ENABLE);
> > + printk_debug("IOR 0x%08X is now 0x%08X\n",
> > + GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
> > + iol = inl(GPIOL_INPUT_INVERT_ENABLE);
> > + printk_debug("IOR 0x%08X is now 0x%08X\n",
> > + GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
> > + iol = inl(GPIO_MAPPER_X);
> > + printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
> > + iol);
> > +#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
> > +}
>
> Yuck. Again a huge pile of code which can't be _that_ board-specific if
> it works for at least two boards (this one and DB800). Should be moved elsewhere
> IMO (but that's probably for an extra patch).
>
>
> > +
> > +static void init(struct device *dev)
> > +{
> > + printk_debug("IEI PCISA-LX ENTER %s\n", __FUNCTION__);
> > + printk_debug("IEI PCISA-LX EXIT %s\n", __FUNCTION__);
> > +}
> > +
> > +static void enable_dev(struct device *dev)
> > +{
> > + dev->ops->init = init;
> > +}
> > +
> > +struct chip_operations mainboard_iei_pcisa_lx_ops = {
> > + CHIP_NAME("IEI PCISA-LX Mainboard")
> > + .enable_dev = enable_dev,
> > +
> > +};
> > diff -Nru LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/Options.lb LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/Options.lb
> > --- LinuxBIOSv2-2986/src/mainboard/iei/pcisa-lx/Options.lb 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/src/mainboard/iei/pcisa-lx/Options.lb 2007-11-26 09:50:43.000000000 +0500
> > @@ -0,0 +1,180 @@
> > +uses HAVE_MP_TABLE
> > +uses HAVE_PIRQ_TABLE
> > +uses USE_FALLBACK_IMAGE
> > +uses HAVE_FALLBACK_BOOT
> > +uses HAVE_HARD_RESET
> > +uses HAVE_OPTION_TABLE
> > +uses USE_OPTION_TABLE
> > +uses CONFIG_ROM_PAYLOAD
> > +uses IRQ_SLOT_COUNT
> > +uses MAINBOARD
> > +uses MAINBOARD_VENDOR
> > +uses MAINBOARD_PART_NUMBER
> > +uses LINUXBIOS_EXTRA_VERSION
> > +uses ARCH
> > +uses FALLBACK_SIZE
> > +uses STACK_SIZE
> > +uses HEAP_SIZE
> > +uses ROM_SIZE
> > +uses ROM_SECTION_SIZE
> > +uses ROM_IMAGE_SIZE
> > +uses ROM_SECTION_SIZE
> > +uses ROM_SECTION_OFFSET
> > +uses CONFIG_ROM_PAYLOAD_START
> > +uses CONFIG_COMPRESS
> > +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
> > +uses CONFIG_COMPRESSED_PAYLOAD_LZMA
> > +uses CONFIG_PRECOMPRESSED_PAYLOAD
> > +uses PAYLOAD_SIZE
> > +uses _ROMBASE
> > +uses _RAMBASE
> > +uses XIP_ROM_SIZE
> > +uses XIP_ROM_BASE
> > +uses HAVE_MP_TABLE
> > +uses CROSS_COMPILE
> > +uses CC
> > +uses HOSTCC
> > +uses OBJCOPY
> > +uses DEFAULT_CONSOLE_LOGLEVEL
> > +uses MAXIMUM_CONSOLE_LOGLEVEL
> > +uses CONFIG_CONSOLE_SERIAL8250
> > +uses TTYS0_BAUD
> > +uses TTYS0_BASE
> > +uses TTYS0_LCS
> > +uses CONFIG_UDELAY_IO
> > +uses CONFIG_CONSOLE_VGA
> > +uses CONFIG_PCI_ROM_RUN
> > +uses CONFIG_VIDEO_MB
> > +uses USE_DCACHE_RAM
> > +uses DCACHE_RAM_BASE
> > +uses DCACHE_RAM_SIZE
> > +uses PIRQ_ROUTE
> > +
> > +## ROM_SIZE is the size of boot ROM that this board will use.
> > +default ROM_SIZE = 256*1024
> > +
> > +###
> > +### Build options
> > +###
> > +default CONFIG_CONSOLE_VGA=0
> > +default CONFIG_VIDEO_MB=8
> > +default CONFIG_PCI_ROM_RUN=0
> > +
> > +##
> > +## Build code for the fallback boot
> > +##
> > +default HAVE_FALLBACK_BOOT=1
> > +
> > +##
> > +## no MP table
> > +##
> > +default HAVE_MP_TABLE=0
> > +
> > +##
> > +## Build code to reset the motherboard from linuxBIOS
> > +##
> > +default HAVE_HARD_RESET=0
> > +
> > +## Delay timer options
> > +##
> > +default CONFIG_UDELAY_IO=1
>
> This is a change from the DB800 target:
>
> -default CONFIG_UDELAY_TSC=1
> -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
> +default CONFIG_UDELAY_IO=1
>
> No TSC or TIMER2 on Geode boards?
With CONFIG_UDELAY_TSC and CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
options boot-up occurs at 2 seconds longer.
>
>
> > +
> > +##
> > +## Build code to export a programmable irq routing table
> > +##
> > +default HAVE_PIRQ_TABLE=1
> > +default IRQ_SLOT_COUNT=9
> > +default PIRQ_ROUTE=1
> > +#object irq_tables.o
> > +
> > +##
> > +## Build code to export a CMOS option table
> > +##
> > +default HAVE_OPTION_TABLE=0
> > +
> > +###
> > +### LinuxBIOS layout values
> > +###
> > +
> > +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
> > +default ROM_IMAGE_SIZE = 65536
> > +default FALLBACK_SIZE = 131072
> > +
> > +##
> > +## enable CACHE_AS_RAM specifics
> > +##
> > +default USE_DCACHE_RAM=1
> > +default DCACHE_RAM_BASE=0xc8000
> > +default DCACHE_RAM_SIZE=0x08000
> > +
> > +##
> > +## Use a small 8K stack
> > +##
> > +default STACK_SIZE=0x2000
> > +
> > +##
> > +## Use a small 16K heap
> > +##
> > +default HEAP_SIZE=0x4000
> > +
> > +##
> > +## Only use the option table in a normal image
> > +##
> > +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
> > +default USE_OPTION_TABLE = 0
> > +
> > +default _RAMBASE = 0x00004000
> > +
> > +default CONFIG_ROM_PAYLOAD = 1
> > +
> > +##
> > +## The default compiler
> > +##
> > +default CROSS_COMPILE=""
> > +default CC="$(CROSS_COMPILE)gcc -m32"
> > +default HOSTCC="gcc"
> > +
> > +##
> > +## The Serial Console
> > +##
> > +
> > +# To Enable the Serial Console
> > +default CONFIG_CONSOLE_SERIAL8250=1
> > +
> > +## Select the serial console baud rate
> > +default TTYS0_BAUD=115200
> > +#default TTYS0_BAUD=57600
> > +#default TTYS0_BAUD=38400
> > +#default TTYS0_BAUD=19200
> > +#default TTYS0_BAUD=9600
> > +#default TTYS0_BAUD=4800
> > +#default TTYS0_BAUD=2400
> > +#default TTYS0_BAUD=1200
> > +
> > +# Select the serial console base port
> > +default TTYS0_BASE=0x3f8
> > +
> > +# Select the serial protocol
> > +# This defaults to 8 data bits, 1 stop bit, and no parity
> > +default TTYS0_LCS=0x3
> > +
> > +##
> > +### Select the linuxBIOS loglevel
> > +##
> > +## EMERG 1 system is unusable
> > +## ALERT 2 action must be taken immediately
> > +## CRIT 3 critical conditions
> > +## ERR 4 error conditions
> > +## WARNING 5 warning conditions
> > +## NOTICE 6 normal but significant condition
> > +## INFO 7 informational
> > +## DEBUG 8 debug-level messages
> > +## SPEW 9 Way too many details
> > +
> > +## Request this level of debugging output
> > +default DEFAULT_CONSOLE_LOGLEVEL=8
> > +## At a maximum only compile in this level of debugging
> > +default MAXIMUM_CONSOLE_LOGLEVEL=8
> > +
> > +end
> > +
> > diff -Nru LinuxBIOSv2-2986/targets/iei/pcisa-lx/Config.lb LinuxBIOSv2-2986-lx/targets/iei/pcisa-lx/Config.lb
> > --- LinuxBIOSv2-2986/targets/iei/pcisa-lx/Config.lb 1970-01-01 05:00:00.000000000 +0500
> > +++ LinuxBIOSv2-2986-lx/targets/iei/pcisa-lx/Config.lb 2007-11-26 10:13:13.000000000 +0500
> > @@ -0,0 +1,43 @@
> > +##
> > +## This file is part of the LinuxBIOS project.
> > +##
> > +## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
> > +##
> > +## This program is free software; you can redistribute it and/or modify
> > +## it under the terms of the GNU General Public License as published by
> > +## the Free Software Foundation; either version 2 of the License, or
> > +## (at your option) any later version.
> > +##
> > +## This program is distributed in the hope that it will be useful,
> > +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > +## GNU General Public License for more details.
> > +##
> > +## You should have received a copy of the GNU General Public License
> > +## along with this program; if not, write to the Free Software
> > +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
> > +##
> > +
> > +target pcisa-lx
> > +mainboard iei/pcisa-lx
> > +
> > +option CONFIG_COMPRESS=0
> > +option CONFIG_PRECOMPRESSED_PAYLOAD=0
> > +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
> > +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
> > +
> > +# Leave 36k for VSA.
> > +option ROM_SIZE=512*1024-36*1024
> > +option FALLBACK_SIZE=ROM_SIZE
> > +
> > +option DEFAULT_CONSOLE_LOGLEVEL = 0
> > +option MAXIMUM_CONSOLE_LOGLEVEL = 0
> > +
> > +romimage "fallback"
> > + option USE_FALLBACK_IMAGE=1
> > + option ROM_IMAGE_SIZE=96*1024
> > + option LINUXBIOS_EXTRA_VERSION=".0Fallback"
> > + payload ../../payload.elf
> > +end
> > +
> > +buildrom ./pcisa-lx.rom ROM_SIZE "fallback"
>
> Keep this "./linuxbios.rom" please, we do that will almost all boards
> and it's a good thing IMO.
>
OK.
>
> HTH, Uwe.
> --
> http://www.hermann-uwe.de | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
>
--
Nikolay
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