[LinuxBIOS] [PATCH] improved SPI flash support (restructured)

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Mon Oct 1 14:53:35 CEST 2007


On 01.10.2007 14:25, Ward Vandewege wrote:
> On Mon, Oct 01, 2007 at 12:28:46PM +0200, Carl-Daniel Hailfinger wrote:
>> Will be implemented once this patch has been tested.
> 
> Ah, yes, sorry, here's the output:

Thanks!

> # ./flashrom 
> Calibrating delay loop... ok
> No LinuxBIOS table found.
> Found chipset "NVIDIA MCP55": Enabling flash write... OK.
> No EEPROM/flash device found.
> 
> # ./flashrom -v
> Calibrating delay loop... ok
> No LinuxBIOS table found.
> Found chipset "NVIDIA MCP55": Enabling flash write... OK.
> No EEPROM/flash device found.
> 
> # ./flashrom -v -m gigabyte:m57sli
> Calibrating delay loop... ok
> No LinuxBIOS table found.
> Found chipset "NVIDIA MCP55": Enabling flash write... OK.
> Found board "GIGABYTE GA-M57SLI": Enabling flash write... Serial flash
> segment 0xfffe0000-0xffffffff enabled
> Serial flash segment 0x000e0000-0x000fffff enabled
> Serial flash segment 0xffee0000-0xffefffff disabled
> Serial flash segment 0xfff80000-0xfffeffff enabled
> LPC write to serial flash enabled
> serial flash pin 29
> OK.
> No EEPROM/flash device found.
> 
> Does that look good?

Unfortunately not. Hmm... you used -v (verify) instead of -V (verbose).
And my patch was incomplete.

Can you try "flashrom -V -m gigabyte:m57sli" with the attached patch
(against current svn) and report back?

Thanks,
Carl-Daniel
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: linuxbios_flashrom_ite_spi_restructured3.diff
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20071001/dcb4b56a/attachment.ksh>


More information about the coreboot mailing list