[LinuxBIOS] r2921 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
svn at openbios.org
svn at openbios.org
Wed Oct 31 01:49:39 CET 2007
Author: hailfinger
Date: 2007-10-31 01:49:38 +0100 (Wed, 31 Oct 2007)
New Revision: 2921
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
Log:
As started in
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html ,
but change all apparantly related values that differ on my board with
legacy BIOS.
This makes both PCI cards appear, as well as the firewire device
TSB43AB23.
* PCI 01:07.0 appears fully functional
* PCI 01:08.0 (closer to the board edge) appears, but no interrupts
* PCI 01:0a.0 (FireWire) untested
Since none of these was even present without the patch I suggest to
apply it.
Signed-off-by: Torsten Duwe <duwe at lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Tested-by: Harald Gutmann <harald.gutmann at gmx.net>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-10-31 00:26:08 UTC (rev 2920)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-10-31 00:49:38 UTC (rev 2921)
@@ -134,10 +134,10 @@
#define MCP55_PCI_E_X_0 0
#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
More information about the coreboot
mailing list