[coreboot] r714 - in coreboot-v3: arch/x86 device mainboard/adl/msm800sev mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/emulation/qemu-x86 mainboard/gigabyte/m57sli mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 northbridge/amd/geodelx northbridge/amd/k8 northbridge/intel/i440bxemulation southbridge/amd/cs5536 southbridge/intel/i82371eb southbridge/nvidia/mcp55 superio/fintek/f71805f superio/ite/it8716f superio/winbond/w83627hf
svn at coreboot.org
svn at coreboot.org
Sat Aug 2 22:56:12 CEST 2008
Author: hailfinger
Date: 2008-08-02 22:56:11 +0200 (Sat, 02 Aug 2008)
New Revision: 714
Modified:
coreboot-v3/arch/x86/Makefile
coreboot-v3/device/Makefile
coreboot-v3/mainboard/adl/msm800sev/Makefile
coreboot-v3/mainboard/amd/db800/Makefile
coreboot-v3/mainboard/amd/norwich/Makefile
coreboot-v3/mainboard/artecgroup/dbe61/Makefile
coreboot-v3/mainboard/artecgroup/dbe62/Makefile
coreboot-v3/mainboard/emulation/qemu-x86/Makefile
coreboot-v3/mainboard/gigabyte/m57sli/Makefile
coreboot-v3/mainboard/pcengines/alix1c/Makefile
coreboot-v3/mainboard/pcengines/alix2c3/Makefile
coreboot-v3/northbridge/amd/geodelx/Makefile
coreboot-v3/northbridge/amd/k8/Makefile
coreboot-v3/northbridge/intel/i440bxemulation/Makefile
coreboot-v3/southbridge/amd/cs5536/Makefile
coreboot-v3/southbridge/intel/i82371eb/Makefile
coreboot-v3/southbridge/nvidia/mcp55/Makefile
coreboot-v3/superio/fintek/f71805f/Makefile
coreboot-v3/superio/ite/it8716f/Makefile
coreboot-v3/superio/winbond/w83627hf/Makefile
Log:
Convert stage2 and initram makefile rules from object to source files.
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/arch/x86/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -178,27 +178,32 @@
# TODO: This should be compressed with the default compressor.
#
-STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
- compute_ip_checksum.o string.o
+STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \
+ compute_ip_checksum.c string.c
-STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
endif
STAGE2_DYNAMIC_OBJ = statictree.o
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
- $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
- $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
- $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
- $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+ $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+ $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+ $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special because the static tree object ends up in the mainboard
+# dir of the object tree.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
# x86emu wants libgcc
@@ -214,7 +219,7 @@
STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
$(Q)# leave a .o with full symbols in it for debugging.
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -260,9 +265,9 @@
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
- $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+ $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
$(Q)# initram links against stage0
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \
Modified: coreboot-v3/device/Makefile
===================================================================
--- coreboot-v3/device/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/device/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
- pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+ pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
Modified: coreboot-v3/mainboard/adl/msm800sev/Makefile
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/amd/db800/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/db800/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/amd/db800/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/amd/norwich/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/norwich/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/amd/norwich/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -28,10 +28,10 @@
# directory and is built from what was auto.c in v2.
#
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
#
# VPD or SIP ROM or... how does NVIDIA call it?
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,9 +21,9 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/mainboard/pcengines/alix2c3/Makefile
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/mainboard/pcengines/alix2c3/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Modified: coreboot-v3/northbridge/amd/geodelx/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/amd/geodelx/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,9 +21,9 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
- $(obj)/northbridge/amd/geodelx/vsmsetup.o \
- $(obj)/util/x86emu/vm86_gdt.o \
- $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+ $(src)/northbridge/amd/geodelx/vsmsetup.c \
+ $(src)/util/x86emu/vm86_gdt.c \
+ $(src)/northbridge/amd/geodelx/grphinit.c
endif
Modified: coreboot-v3/northbridge/amd/k8/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/k8/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/amd/k8/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,6 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/k8/raminit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/raminit.c
endif
Modified: coreboot-v3/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/northbridge/intel/i440bxemulation/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,6 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
endif
Modified: coreboot-v3/southbridge/amd/cs5536/Makefile
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/amd/cs5536/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,10 +21,10 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
Modified: coreboot-v3/southbridge/intel/i82371eb/Makefile
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/intel/i82371eb/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -20,6 +20,6 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
endif
Modified: coreboot-v3/southbridge/nvidia/mcp55/Makefile
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/southbridge/nvidia/mcp55/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -21,10 +21,10 @@
ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/mcp55.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/mcp55.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/irq_tables.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/irq_tables.c
endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o
Modified: coreboot-v3/superio/fintek/f71805f/Makefile
===================================================================
--- coreboot-v3/superio/fintek/f71805f/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/fintek/f71805f/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
endif
Modified: coreboot-v3/superio/ite/it8716f/Makefile
===================================================================
--- coreboot-v3/superio/ite/it8716f/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/ite/it8716f/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -24,6 +24,6 @@
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c
endif
Modified: coreboot-v3/superio/winbond/w83627hf/Makefile
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/Makefile 2008-08-02 03:34:05 UTC (rev 713)
+++ coreboot-v3/superio/winbond/w83627hf/Makefile 2008-08-02 20:56:11 UTC (rev 714)
@@ -25,6 +25,6 @@
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
endif
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