[coreboot] r749 - coreboot-v3/northbridge/amd/k8
svn at coreboot.org
svn at coreboot.org
Tue Aug 12 01:55:12 CEST 2008
Author: rminnich
Date: 2008-08-12 01:55:10 +0200 (Tue, 12 Aug 2008)
New Revision: 749
Added:
coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c
coreboot-v3/northbridge/amd/k8/incoherent_ht.c
coreboot-v3/northbridge/amd/k8/northbridge.c
Modified:
coreboot-v3/northbridge/amd/k8/Makefile
coreboot-v3/northbridge/amd/k8/raminit.c
Log:
New code as part of bringing things over.
Again, some of this is verbatim from v2, we can change the form later
please.
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Marc Jones <marc.jones at amd.com>
Modified: coreboot-v3/northbridge/amd/k8/Makefile
===================================================================
--- coreboot-v3/northbridge/amd/k8/Makefile 2008-08-11 23:19:53 UTC (rev 748)
+++ coreboot-v3/northbridge/amd/k8/Makefile 2008-08-11 23:55:10 UTC (rev 749)
@@ -22,5 +22,7 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
# no stage2 sources yet.
-STAGE2_CHIPSET_SRC +=
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/get_sblk_pci1234.c \
+ $(src)/northbridge/amd/k8/northbridge.c \
+
endif
Added: coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c (rev 0)
+++ coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c 2008-08-11 23:55:10 UTC (rev 749)
@@ -0,0 +1,280 @@
+/*============================================================================
+Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+This software and any related documentation (the "Materials") are the
+confidential proprietary information of AMD. Unless otherwise provided in a
+software agreement specifically licensing the Materials, the Materials are
+provided in confidence and may not be distributed, modified, or reproduced in
+whole or in part by any means.
+LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
+EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
+WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
+PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
+USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
+DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
+BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
+INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
+OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
+LIMITATION MAY NOT APPLY TO YOU.
+AMD does not assume any responsibility for any errors which may appear in the
+Materials nor any responsibility to support or update the Materials. AMD
+retains the right to modify the Materials at any time, without notice, and is
+not obligated to provide such modified Materials to you.
+NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+further information, software, technical information, know-how, or show-how
+available to you.
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
+RIGHTS." Use, duplication, or disclosure by the Government is subject to the
+restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
+its successor. Use of the Materials by the Government constitutes
+acknowledgement of AMD's proprietary rights in them.
+============================================================================*/
+/* Copyright 2007 coresystems GmbH */
+
+// 2005.9 yhlu serengeti support
+// 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+// 2007.9 stepan improve code documentation
+
+#include <console.h>
+#include <mtrr.h>
+#include <macros.h>
+#include <spd.h>
+#include <cpu.h>
+#include <msr.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
+#include <device/pci.h>
+#include <device/hypertransport_def.h>
+#include <mc146818rtc.h>
+#include <lib.h>
+
+
+#if 0
+unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ struct device * dev;
+ unsigned reg;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ if (!dev) {
+ return 0;
+ }
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ u32 config_map;
+ unsigned dst_node;
+ unsigned dst_link;
+ unsigned bus_base;
+ config_map = pci_read_config32(dev, reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ dst_node = (config_map >> 4) & 7;
+ dst_link = (config_map >> 8) & 3;
+ bus_base = (config_map >> 16) & 0xff;
+#if 0
+ printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+ dst_node, dst_link, bus_base,
+ reg, config_map);
+#endif
+ if ((dst_node == node) && (dst_link == link))
+ {
+ return bus_base;
+ }
+ }
+ return 0;
+}
+#endif
+
+
+/**
+ * Why we need the pci1234[] array
+ *
+ * It will keep the sequence of HT devices in the HT link registers even when a
+ * given HT I/O card is not installed.
+ *
+ * The final result for pci1234[] will be
+ *
+ * pci1234[0] will record the south bridge link and bus range
+ * pci1234[i] will record HT chain i.
+ *
+ * For example, on the Tyan S2885 linxbios_ram will put the AMD8151 chain (HT
+ * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the
+ * register 0xE4.
+ *
+ * So we need to make sure that the south bridge link will always be on
+ * pci1234[0].
+ *
+ * Imagine a scenario with multiple HT I/O cards, where you don't install HT I/O 1,
+ * but you only install HT I/O 2 and HT I/O 3. The HT I/Os will end up in registers
+ * 0xE4 and 0xE8.
+ *
+ * But we want to leave pci1234[1] to HT I/O 1 (even though it is disabled),
+ * and let HT I/O 2 and HT I/O 3 still use pci1234[2] and pci1234[3].
+ *
+ * So we keep the sequence. You need to preset the pci1234[1], pci1234[2],
+ * pci1234[3] for this purpose.
+ *
+ * For this example you need to set
+ *
+ * unsigned pci1234[] = {
+ * 0x0000ff0,
+ * 0x0000f10, // HT IO 1 card always on node 1
+ * 0x0000f20, // HT IO 2 card always on node 2
+ * 0x0000f30 // HT IO 3 card always on node 3
+ * };
+ *
+ * For 2P + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P + htio(n2) + htio(n3):
+ * You need an array pci1234[6]:
+ *
+ * unsigned pci1234[] = {
+ * 0x0000ff0,
+ * 0x0000010, // HT IO 1 card always on node 1
+ * 0x0000f00, // HT IO 2 card always on node 0
+ * 0x0000110, // HT IO 3 card always on node 1
+ * 0x0000f20, // HT IO 4 card always on node 2
+ * 0x0000f30 // HT IO 5 card always on node 3
+ * };
+ *
+ *
+ * For 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7):
+ * You need an array pci1234[6]:
+ *
+ * unsigned pci1234[] = {
+ * 0x0000ff0,
+ * 0x0000f10, // HT IO 1 card always on node 1
+ * 0x0000f20, // HT IO 2 card always on node 2
+ * 0x0000f30, // HT IO 3 card always on node 3
+ * 0x0000f60, // HT IO 4 card always on node 6
+ * 0x0000f70 // HT IO 5 card always on node 7
+ * };
+ *
+ *
+ * For 2p + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P +
+ * htio(n2) + htio(n3), 2P + htio(n1) + 4P + htio(n4) + htio(n5),
+ * you need an array pci1234[8]:
+ *
+ * unsigned pci1234[] = {
+ * 0x0000ff0,
+ * 0x0000010, // HT IO 1 card always on node 1
+ * 0x0000f00, // HT IO 2 card always on node 0
+ * 0x0000110, // HT IO 3 card always on node 1
+ * 0x0000f20, // HT IO 4 card always on node 2
+ * 0x0000f30 // HT IO 5 card always on node 3
+ * 0x0000f40, // HT IO 6 card always on node 4
+ * 0x0000f50 // HT IO 7 card always on node 5
+ * };
+ *
+ *
+ * For 4P + htio(n1) + htio(n2) + htio(n3), 4p + htio(n1) + 2p + htio(n4) +
+ * htio(n5), 4p + htio(n1) + 4p + htio(n6) + htio(n7),
+ * you need an array pci1234[8]:
+ *
+ * unsigned pci1234[] = {
+ * 0x0000ff0,
+ * 0x0000f10, // HT IO 1 card always on node 1
+ * 0x0000f20, // HT IO 2 card always on node 2
+ * 0x0000f30, // HT IO 3 card always on node 3
+ * 0x0000f40, // HT IO 4 card always on node 4
+ * 0x0000f50 // HT IO 5 card always on node 5
+ * 0x0000f60, // HT IO 6 card always on node 6
+ * 0x0000f70 // HT IO 7 card always on node 7
+ * };
+ *
+ *
+ * So the maximum posible value of HC_POSSIBLE_NUM is 8. (FIXME Why?)
+ *
+ * 1n: 3
+ * 2n: 2x2 - 1
+ * 4n: 1x4 - 2
+ * 6n: 2
+ * 8n: 2
+ * Total: 12
+ *
+ * Just put all the possible HT Node/link to the list tp pci1234[] in
+ * src/mainboard/<vendor>/<mainboard>get_bus_conf.c
+ *
+ * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if
+ * you have too many SSDTs
+ *
+ * What about co-processor in socket 1 on a 2 way system? Or socket 2 and
+ * socket 3 on a 4 way system? Treat that as an HC, too!
+ *
+ */
+
+void get_sblk_pci1234(void)
+{
+
+ struct device * dev;
+ int i,j;
+ u32 dword;
+
+ /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+ dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
+ dword = pci_read_config32(dev, 0x64);
+ sysconf.sblk = (dword>>8) & 0x3;
+
+ dword &=0x0300;
+ dword |= 1;
+ sysconf.pci1234[0] = dword;
+ sysconf.hcid[0] = 0;
+
+ /* About hardcoded numbering for HT_IO support
+ *
+ * Set the node_id and link_id that could have a HT chain in the one
+ * array, (FIXME: which one?) then check if is enabled. Then update
+ * final value
+ */
+
+ /* Here we need to set hcdn
+ *
+ * 1. hypertransport.c needs to record hcdn_reg together with 0xe0,
+ * 0xe4, 0xe8, 0xec when are set (FIXME: when WHAT is set?)
+ *
+ * 2. So at the same time we need update hcdn with hcdn_reg here. FIXME: Why?
+ */
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+
+ for(j=0;j<4;j++) {
+ u32 dwordx;
+ dwordx = pci_read_config32(dev, 0xe0 + j*4);
+ dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
+ if((dwordx & 0xff1) == dword) { /* SBLINK */
+ sysconf.pci1234[0] = dwordx;
+ sysconf.hcdn[0] = sysconf.hcdn_reg[j];
+ continue;
+ }
+
+ if((dwordx & 1) == 1) {
+ /* We need to find out the number of HC
+ * for exact match
+ */
+ for(i=1;i<sysconf.hc_possible_num;i++) {
+ if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
+ sysconf.pci1234[i] = dwordx;
+ sysconf.hcdn[i] = sysconf.hcdn_reg[j];
+ break;
+ }
+ }
+
+ /* For 0xff0 match or same node */
+ for(i=1;i<sysconf.hc_possible_num;i++) {
+ if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
+ sysconf.pci1234[i] = dwordx;
+ sysconf.hcdn[i] = sysconf.hcdn_reg[j];
+ break;
+ }
+ }
+ }
+ }
+
+ for(i=1;i<sysconf.hc_possible_num;i++) {
+ if((sysconf.pci1234[i] & 1) != 1) {
+ sysconf.pci1234[i] = 0;
+ sysconf.hcdn[i] = 0x20202020;
+ }
+ sysconf.hcid[i] = 0;
+ }
+
+}
+
Added: coreboot-v3/northbridge/amd/k8/incoherent_ht.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/incoherent_ht.c (rev 0)
+++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-11 23:55:10 UTC (rev 749)
@@ -0,0 +1,918 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ * Copyright (C) 2004 YingHai Lu
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+/*
+ This should be done by Eric
+ 2004.12 yhlu add multi ht chain dynamically support
+ 2005.11 yhlu add let real sb to use small unitid
+*/
+#include <console.h>
+#include <mtrr.h>
+#include <macros.h>
+#include <spd.h>
+#include <cpu.h>
+#include <msr.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
+#include <device/pci.h>
+#include <device/hypertransport_def.h>
+#include <mc146818rtc.h>
+#include <lib.h>
+#include "stage1.h"
+
+static void print_linkn_in (const char *strval, u8 byteval)
+{
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
+}
+
+u8 ht_lookup_capability(u32 bdf, u16 val)
+{
+ u8 pos;
+ u8 hdr_type;
+
+ hdr_type = pci_read_config8(bdf, PCI_HEADER_TYPE);
+ pos = 0;
+ hdr_type &= 0x7f;
+
+ if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
+ (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
+ pos = PCI_CAPABILITY_LIST;
+ }
+ if (pos > PCI_CAP_LIST_NEXT) {
+ pos = pci_read_config8(bdf, pos);
+ }
+ while(pos != 0) { /* loop through the linked list */
+ u8 cap;
+ cap = pci_read_config8(bdf, pos + PCI_CAP_LIST_ID);
+ if (cap == PCI_CAP_ID_HT) {
+ u16 flags;
+
+ flags = pci_read_config16(bdf, pos + PCI_CAP_FLAGS);
+ if ((flags >> 13) == val) {
+ /* Entry is a slave or host , success... */
+ break;
+ }
+ }
+ pos = pci_read_config8(bdf, pos + PCI_CAP_LIST_NEXT);
+ }
+ return pos;
+}
+
+static u8 ht_lookup_slave_capability(u32 bdf)
+{
+ return ht_lookup_capability(bdf, 0); // Slave/Primary Interface Block Format
+}
+
+static u8 ht_lookup_host_capability(u32 bdf)
+{
+ return ht_lookup_capability(bdf, 1); // Host/Secondary Interface Block Format
+}
+
+static void ht_collapse_previous_enumeration(u8 bus, unsigned offset_unitid)
+{
+ u32 bdf;
+ u32 id;
+
+ //actually, only for one HT device HT chain, and unitid is 0
+#if CONFIG_HT_CHAIN_UNITID_BASE == 0
+ if(offset_unitid) {
+ return;
+ }
+#endif
+
+ /* Check if is already collapsed */
+ if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
+ bdf = PCI_BDF(bus, 0, 0);
+ id = pci_read_config32(bdf, PCI_VENDOR_ID);
+ if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
+ (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
+ return;
+ }
+ }
+
+ /* Spin through the devices and collapse any previous
+ * hypertransport enumeration.
+ */
+ for(bdf = PCI_BDF(bus, 1, 0); bdf <= PCI_BDF(bus, 0x1f, 0x7); bdf += PCI_BDF(0, 1, 0)) {
+ u32 id;
+ u8 pos;
+ u16 flags;
+
+ id = pci_read_config32(bdf, PCI_VENDOR_ID);
+ if ((id == 0xffffffff) || (id == 0x00000000) ||
+ (id == 0x0000ffff) || (id == 0xffff0000)) {
+ continue;
+ }
+
+ pos = ht_lookup_slave_capability(bdf);
+ if (!pos) {
+ continue;
+ }
+
+ /* Clear the unitid */
+ flags = pci_read_config16(bdf, pos + PCI_CAP_FLAGS);
+ flags &= ~0x1f;
+ pci_write_config16(bdf, pos + PCI_CAP_FLAGS, flags);
+ }
+}
+
+static u16 ht_read_freq_cap(u32 bdf, u8 pos)
+{
+ /* Handle bugs in valid hypertransport frequency reporting */
+ u16 freq_cap;
+ u32 id;
+
+ freq_cap = pci_read_config16(bdf, pos);
+ freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
+
+ id = pci_read_config32(bdf, 0);
+
+ /* AMD 8131 Errata 48 */
+ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) {
+ freq_cap &= ~(1 << HT_FREQ_800Mhz);
+ return freq_cap;
+ }
+
+ /* AMD 8151 Errata 23 */
+ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8151_SYSCTRL << 16))) {
+ freq_cap &= ~(1 << HT_FREQ_800Mhz);
+ return freq_cap;
+ }
+
+ /* AMD K8 Unsupported 1Ghz? */
+ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
+ #if K8_HT_FREQ_1G_SUPPORT == 1
+ #if K8_REV_F_SUPPORT == 0
+ if (is_cpu_pre_e0()) { // only E0 later support 1GHz
+ freq_cap &= ~(1 << HT_FREQ_1000Mhz);
+ }
+ #endif
+ #else
+ freq_cap &= ~(1 << HT_FREQ_1000Mhz);
+ #endif
+ }
+
+ return freq_cap;
+}
+static u8 ht_read_width_cap(u32 bdf, u8 pos)
+{
+ u8 width_cap = pci_read_config8(bdf, pos);
+
+ u32 id;
+
+ id = pci_read_config32(bdf, 0);
+
+ /* netlogic micro cap doesn't support 16 bit yet */
+ if (id == (0x184e | (0x0001 << 16))) {
+ if((width_cap & 0x77) == 0x11) {
+ width_cap &= 0x88;
+ }
+ }
+
+ return width_cap;
+
+}
+#define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
+ (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
+
+#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF)
+#define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF)
+#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF)
+#define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
+
+#define PCI_HT_HOST_OFFS LINK_OFFS( \
+ PCI_HT_CAP_HOST_CTRL, \
+ PCI_HT_CAP_HOST_WIDTH, \
+ PCI_HT_CAP_HOST_FREQ, \
+ PCI_HT_CAP_HOST_FREQ_CAP)
+
+#define PCI_HT_SLAVE0_OFFS LINK_OFFS( \
+ PCI_HT_CAP_SLAVE_CTRL0, \
+ PCI_HT_CAP_SLAVE_WIDTH0, \
+ PCI_HT_CAP_SLAVE_FREQ0, \
+ PCI_HT_CAP_SLAVE_FREQ_CAP0)
+
+#define PCI_HT_SLAVE1_OFFS LINK_OFFS( \
+ PCI_HT_CAP_SLAVE_CTRL1, \
+ PCI_HT_CAP_SLAVE_WIDTH1, \
+ PCI_HT_CAP_SLAVE_FREQ1, \
+ PCI_HT_CAP_SLAVE_FREQ_CAP1)
+
+static int ht_optimize_link(
+ u32 bdf1, u8 pos1, unsigned offs1,
+ u32 bdf2, u8 pos2, unsigned offs2)
+{
+ static const u8 link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
+ static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
+ u16 freq_cap1, freq_cap2;
+ u8 width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
+ u8 freq, old_freq;
+ int needs_reset;
+ /* Set link width and frequency */
+
+ /* Initially assume everything is already optimized and I don't need a reset */
+ needs_reset = 0;
+
+ /* Get the frequency capabilities */
+ freq_cap1 = ht_read_freq_cap(bdf1, pos1 + LINK_FREQ_CAP(offs1));
+ freq_cap2 = ht_read_freq_cap(bdf2, pos2 + LINK_FREQ_CAP(offs2));
+
+ /* Calculate the highest possible frequency */
+ freq = log2(freq_cap1 & freq_cap2);
+
+ /* See if I am changing the link freqency */
+ old_freq = pci_read_config8(bdf1, pos1 + LINK_FREQ(offs1));
+ old_freq &= 0x0f;
+ needs_reset |= old_freq != freq;
+ old_freq = pci_read_config8(bdf2, pos2 + LINK_FREQ(offs2));
+ old_freq &= 0x0f;
+ needs_reset |= old_freq != freq;
+
+ /* Set the Calulcated link frequency */
+ pci_write_config8(bdf1, pos1 + LINK_FREQ(offs1), freq);
+ pci_write_config8(bdf2, pos2 + LINK_FREQ(offs2), freq);
+
+ /* Get the width capabilities */
+ width_cap1 = ht_read_width_cap(bdf1, pos1 + LINK_WIDTH(offs1));
+ width_cap2 = ht_read_width_cap(bdf2, pos2 + LINK_WIDTH(offs2));
+
+ /* Calculate dev1's input width */
+ ln_width1 = link_width_to_pow2[width_cap1 & 7];
+ ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
+ if (ln_width1 > ln_width2) {
+ ln_width1 = ln_width2;
+ }
+ width = pow2_to_link_width[ln_width1];
+ /* Calculate dev1's output width */
+ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
+ ln_width2 = link_width_to_pow2[width_cap2 & 7];
+ if (ln_width1 > ln_width2) {
+ ln_width1 = ln_width2;
+ }
+ width |= pow2_to_link_width[ln_width1] << 4;
+
+ /* See if I am changing dev1's width */
+ old_width = pci_read_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1);
+ old_width &= 0x77;
+ needs_reset |= old_width != width;
+
+ /* Set dev1's widths */
+ pci_write_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1, width);
+
+ /* Calculate dev2's width */
+ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
+
+ /* See if I am changing dev2's width */
+ old_width = pci_read_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1);
+ old_width &= 0x77;
+ needs_reset |= old_width != width;
+
+ /* Set dev2's widths */
+ pci_write_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1, width);
+
+ return needs_reset;
+}
+
+void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
+ unsigned offset_unitid, struct sys_info *sysinfo);
+
+int scan_pci_bus( unsigned bus , struct sys_info *sysinfo)
+{
+ /*
+ here we already can access PCI_DEV(bus, 0, 0) to PCI_DEV(bus, 0x1f, 0x7)
+ So We can scan these devices to find out if they are bridge
+ If it is pci bridge, We need to set busn in bridge, and go on
+ For ht bridge, We need to set the busn in bridge and ht_setup_chainx, and the scan_pci_bus
+ */
+ unsigned int devfn;
+ unsigned new_bus;
+ unsigned max_bus;
+
+ new_bus = (bus & 0xff); // mask out the reset_needed
+
+ if(new_bus<0x40) {
+ max_bus = 0x3f;
+ } else if (new_bus<0x80) {
+ max_bus = 0x7f;
+ } else if (new_bus<0xc0) {
+ max_bus = 0xbf;
+ } else {
+ max_bus = 0xff;
+ }
+
+ new_bus = bus;
+
+ for (devfn = 0; devfn <= 0xff; devfn++) {
+ u8 hdr_type;
+ u16 class;
+ u32 buses;
+ u32 bdf;
+ u16 cr;
+ bdf = PCI_BDF((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7));
+ hdr_type = pci_read_config8(bdf, PCI_HEADER_TYPE);
+ class = pci_read_config16(bdf, PCI_CLASS_DEVICE);
+
+ switch(hdr_type & 0x7f) { /* header type */
+ case PCI_HEADER_TYPE_BRIDGE:
+ if (class != PCI_CLASS_BRIDGE_PCI) goto bad;
+ /* set the bus range dev */
+
+ /* Clear all status bits and turn off memory, I/O and master enables. */
+ cr = pci_read_config16(bdf, PCI_COMMAND);
+ pci_write_config16(bdf, PCI_COMMAND, 0x0000);
+ pci_write_config16(bdf, PCI_STATUS, 0xffff);
+
+ buses = pci_read_config32(bdf, PCI_PRIMARY_BUS);
+
+ buses &= 0xff000000;
+ new_bus++;
+ buses |= (((unsigned int) (bus & 0xff) << 0) |
+ ((unsigned int) (new_bus & 0xff) << 8) |
+ ((unsigned int) max_bus << 16));
+ pci_write_config32(bdf, PCI_PRIMARY_BUS, buses);
+
+ /* here we need to figure out if dev is a ht bridge
+ if it is ht bridge, we need to call ht_setup_chainx at first
+ Not verified --- yhlu
+ */
+ u8 upos;
+ upos = ht_lookup_host_capability(bdf); // one func one ht sub
+ if (upos) { // sub ht chain
+ u8 busn;
+ busn = (new_bus & 0xff);
+ /* Make certain the HT bus is not enumerated */
+ ht_collapse_previous_enumeration(busn, 0);
+ /* scan the ht chain */
+ ht_setup_chainx(bdf,upos,busn, 0, sysinfo); // don't need offset unitid
+ }
+
+ new_bus = scan_pci_bus(new_bus, sysinfo);
+ /* set real max bus num in that */
+
+ buses = (buses & 0xff00ffff) |
+ ((unsigned int) (new_bus & 0xff) << 16);
+ pci_write_config32(bdf, PCI_PRIMARY_BUS, buses);
+
+ pci_write_config16(bdf, PCI_COMMAND, cr);
+
+ break;
+ default:
+ bad:
+ ;
+ }
+
+ /* if this is not a multi function device,
+ * or the device is not present don't waste
+ * time probing another function.
+ * Skip to next device.
+ */
+ if ( ((devfn & 0x07) == 0x00) && ((hdr_type & 0x80) != 0x80))
+ {
+ devfn += 0x07;
+ }
+ }
+
+ return new_bus;
+}
+
+void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
+ unsigned offset_unitid, struct sys_info *sysinfo)
+{
+ //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
+
+ u8 next_unitid, last_unitid;
+ unsigned uoffs;
+
+ int reset_needed = 0;
+
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ /* let's record the device of last ht device,
+ * So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
+ */
+ unsigned real_last_unitid;
+ u8 real_last_pos;
+ int ht_dev_num = 0;
+ u8 end_used = 0;
+#endif
+
+ uoffs = PCI_HT_HOST_OFFS;
+ next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
+
+ do {
+ u32 id;
+ u8 pos;
+ u16 flags, ctrl;
+ u8 count;
+ unsigned offs;
+
+ /* Wait until the link initialization is complete */
+ do {
+ ctrl = pci_read_config16(bdf, upos + LINK_CTRL(uoffs));
+ /* Is this the end of the hypertransport chain? */
+ if (ctrl & (1 << 6)) {
+ goto end_of_chain;
+ }
+
+ if (ctrl & ((1 << 4) | (1 << 8))) {
+ /*
+ * Either the link has failed, or we have
+ * a CRC error.
+ * Sometimes this can happen due to link
+ * retrain, so lets knock it down and see
+ * if its transient
+ */
+ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
+ pci_write_config16(bdf, upos + LINK_CTRL(uoffs), ctrl);
+ ctrl = pci_read_config16(bdf, upos + LINK_CTRL(uoffs));
+ if (ctrl & ((1 << 4) | (1 << 8))) {
+ printk(BIOS_ERR, "Detected error on Hypertransport Link\n");
+ break;
+ }
+ }
+ } while((ctrl & (1 << 5)) == 0);
+
+ u32 abdf = PCI_BDF(bus, 0, 0);
+ last_unitid = next_unitid;
+
+ id = pci_read_config32(abdf, PCI_VENDOR_ID);
+
+ /* If the chain is enumerated quit */
+ if ( (id == 0xffffffff) || (id == 0x00000000) ||
+ (id == 0x0000ffff) || (id == 0xffff0000))
+ {
+ break;
+ }
+
+ pos = ht_lookup_slave_capability(abdf);
+ if (!pos) {
+ printk(BIOS_ERR, "udev=%08x upos = %08x uoffs = %08x",
+ bdf, upos, uoffs);
+ printk(BIOS_ERR, ": HT link capability not found\n");
+
+ }
+
+
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ if(offset_unitid) {
+ if(next_unitid>= (bus ? 0x20:0x18) ) {
+ if(!end_used) {
+ next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
+ end_used = 1;
+ } else {
+ goto out;
+ }
+
+ }
+ real_last_pos = pos;
+ real_last_unitid = next_unitid;
+ ht_dev_num++;
+ }
+#endif
+ /* Update the Unitid of the current device */
+ flags = pci_read_config16(abdf, pos + PCI_CAP_FLAGS);
+ flags &= ~0x1f; /* mask out the base Unit ID */
+ flags |= next_unitid & 0x1f;
+ pci_write_config16(abdf, pos + PCI_CAP_FLAGS, flags);
+
+ /* Compute the number of unitids consumed */
+ count = (flags >> 5) & 0x1f;
+
+ /* Note the change in device number */
+ abdf = PCI_BDF(bus, next_unitid, 0);
+
+ next_unitid += count;
+
+ /* Find which side of the ht link we are on,
+ * by reading which direction our last write to PCI_CAP_FLAGS
+ * came from.
+ */
+ flags = pci_read_config16(abdf, pos + PCI_CAP_FLAGS);
+ offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
+
+ /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
+ {
+ struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
+ link_pair->udev = bdf;
+ link_pair->upos = upos;
+ link_pair->uoffs = uoffs;
+ link_pair->dev = abdf;
+ link_pair->pos = pos;
+ link_pair->offs = offs;
+ sysinfo->link_pair_num++;
+ }
+
+ /* Remeber the location of the last device */
+ bdf = abdf;
+ upos = pos;
+ uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
+
+ } while (last_unitid != next_unitid );
+
+out:
+end_of_chain: ;
+
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
+ u16 flags;
+ int i;
+ flags = pci_read_config16(PCI_BDF(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
+ flags &= ~0x1f;
+ flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
+ pci_write_config16(PCI_BDF(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
+
+ // Here need to change the dev in the array
+ for(i=0;i<sysinfo->link_pair_num;i++)
+ {
+ struct link_pair_st *link_pair = &sysinfo->link_pair[i];
+ if(link_pair->udev == PCI_BDF(bus, real_last_unitid, 0)) {
+ link_pair->udev = PCI_BDF(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
+ continue;
+ }
+ if(link_pair->dev == PCI_BDF(bus, real_last_unitid, 0)) {
+ link_pair->dev = PCI_BDF(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0);
+ }
+ }
+
+ }
+#endif
+
+}
+
+void ht_setup_chain(u32 bdf, unsigned upos, struct sys_info *sysinfo)
+{
+ unsigned offset_unitid = 0;
+#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ offset_unitid = 1;
+#endif
+
+ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
+ * On most boards this just happens. If a cpu has multiple
+ * non Coherent links the appropriate bus registers for the
+ * links needs to be programed to point at bus 0.
+ */
+
+ /* Make certain the HT bus is not enumerated */
+ ht_collapse_previous_enumeration(0, 0);
+
+#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ offset_unitid = 1;
+#endif
+
+ ht_setup_chainx(bdf, upos, 0, offset_unitid, sysinfo);
+}
+
+int optimize_link_read_pointer(u8 node, u8 linkn, u8 linkt, u8 val)
+{
+ u32 dword, dword_old;
+ u8 link_type;
+
+ /* This works on an Athlon64 because unimplemented links return 0 */
+ dword = pci_read_config32(PCI_BDF(0,0x18+node,0), 0x98 + (linkn * 0x20));
+ link_type = dword & 0xff;
+
+
+ if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ dword_old = dword = pci_read_config32(PCI_BDF(0,0x18+node,3), 0xdc);
+ dword &= ~( 0xff<<(linkn *8) );
+ dword |= val << (linkn *8);
+
+ if (dword != dword_old) {
+ pci_write_config32(PCI_BDF(0,0x18+node,3), 0xdc, dword);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static int optimize_link_read_pointers_chain(u8 ht_c_num)
+{
+ int reset_needed;
+ u8 i;
+
+ reset_needed = 0;
+
+ for (i = 0; i < ht_c_num; i++) {
+ u32 reg;
+ u8 nodeid, linkn;
+ u8 busn;
+ u8 val;
+ unsigned devn = 1;
+
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ if(i==0) // to check if it is sb ht chain
+ #endif
+ devn = CONFIG_HT_CHAIN_UNITID_BASE;
+ #endif
+
+ reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);
+
+ nodeid = ((reg & 0xf0)>>4); // nodeid
+ linkn = ((reg & 0xf00)>>8); // link n
+ busn = (reg & 0xff0000)>>16; //busn
+
+ reg = pci_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
+ if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) {
+ val = 0x25;
+ } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) {
+ val = 0x25;//???
+ } else {
+ continue;
+ }
+
+ reset_needed |= optimize_link_read_pointer(nodeid, linkn, 0x07, val);
+
+ }
+
+ return reset_needed;
+}
+
+int set_ht_link_buffer_count(u8 node, u8 linkn, u8 linkt, unsigned val)
+{
+ u32 dword;
+ u8 link_type;
+ unsigned regpos;
+ u32 bdf;
+
+ /* This works on an Athlon64 because unimplemented links return 0 */
+ regpos = 0x98 + (linkn * 0x20);
+ bdf = PCI_BDF(0,0x18+node,0);
+ dword = pci_read_config32(bdf, regpos);
+ link_type = dword & 0xff;
+
+ if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ regpos = 0x90 + (linkn * 0x20);
+ dword = pci_read_config32(bdf, regpos );
+
+ if (dword != val) {
+ pci_write_config32(bdf, regpos, val);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val)
+{
+ int reset_needed;
+ u8 i;
+
+ reset_needed = 0;
+
+ for (i = 0; i < ht_c_num; i++) {
+ u32 reg;
+ u8 nodeid, linkn;
+ u8 busn;
+ unsigned devn;
+
+ reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);
+ if((reg & 3) != 3) continue; // not enabled
+
+ nodeid = ((reg & 0xf0)>>4); // nodeid
+ linkn = ((reg & 0xf00)>>8); // link n
+ busn = (reg & 0xff0000)>>16; //busn
+
+ for(devn = 0; devn < 0x20; devn++) {
+ reg = pci_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); //1?
+ if ( (reg & 0xffff) == vendorid ) {
+ reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
+ break;
+ }
+ }
+ }
+
+ return reset_needed;
+}
+
+
+static void ht_setup_chains(u8 ht_c_num, struct sys_info *sysinfo)
+{
+ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
+ * On most boards this just happens. If a cpu has multiple
+ * non Coherent links the appropriate bus registers for the
+ * links needs to be programed to point at bus 0.
+ */
+ u8 upos;
+ u32 ubdf;
+ u8 i;
+
+ sysinfo->link_pair_num = 0;
+
+ // first one is SB Chain
+ for (i = 0; i < ht_c_num; i++) {
+ u32 reg;
+ u8 devpos;
+ unsigned regpos;
+ u32 dword;
+ u8 busn;
+ unsigned bus;
+ unsigned offset_unitid = 0;
+
+ reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);
+
+ //We need setup 0x94, 0xb4, and 0xd4 according to the reg
+ devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
+ regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
+ busn = (reg & 0xff0000)>>16;
+
+ dword = pci_read_config32( PCI_BDF(0, devpos, 0), regpos) ;
+ dword &= ~(0xffff<<8);
+ dword |= (reg & 0xffff0000)>>8;
+ pci_write_config32( PCI_BDF(0, devpos,0), regpos , dword);
+
+
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ if(i==0) // to check if it is sb ht chain
+ #endif
+ offset_unitid = 1;
+ #endif
+
+ /* Make certain the HT bus is not enumerated */
+ ht_collapse_previous_enumeration(busn, offset_unitid);
+
+ upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
+ ubdf = PCI_BDF(0, devpos, 0);
+
+ ht_setup_chainx(ubdf,upos,busn, offset_unitid, sysinfo); // all not
+
+ #if (CONFIG_K8_SCAN_PCI_BUS == 1)
+ bus = busn; // we need 32 bit
+ scan_pci_bus(bus, sysinfo);
+ #endif
+ }
+
+}
+
+unsigned get_nodes(void);
+
+void ht_setup_chains_x(struct sys_info *sysinfo)
+{
+ unsigned int get_sbdn(unsigned int bus);
+ u8 nodeid;
+ u32 reg;
+ u32 tempreg;
+ u8 next_busn;
+ u8 ht_c_num;
+ u8 nodes;
+#if CONFIG_K8_ALLOCATE_IO_RANGE == 1
+ unsigned next_io_base;
+#endif
+
+ nodes = get_nodes();
+
+ /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 0), 0x64);
+ /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
+ print_linkn_in("SBLink=", ((reg>>8) & 3) );
+ sysinfo->sblk = (reg>>8) & 3;
+ sysinfo->sbbusn = 0;
+ sysinfo->nodes = nodes;
+ tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0, tempreg);
+
+ next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
+
+#if CONFIG_K8_ALLOCATE_IO_RANGE == 1
+ /* io range allocation */
+ tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC4, tempreg);
+ tempreg = 3 | ( 3<<4) | (0<<12); //base
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC0, tempreg);
+ next_io_base = 0x3+0x1;
+#endif
+
+ /* clean others */
+ for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
+
+#if CONFIG_K8_ALLOCATE_IO_RANGE == 1
+ /* io range allocation */
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
+#endif
+ }
+
+ for(nodeid=0; nodeid<nodes; nodeid++) {
+ u32 bdf;
+ u8 linkn;
+ bdf = PCI_BDF(0, 0x18+nodeid,0);
+ for(linkn = 0; linkn<3; linkn++) {
+ unsigned regpos;
+ regpos = 0x98 + 0x20 * linkn;
+ reg = pci_read_config32(bdf, regpos);
+ if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/
+ print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
+ tempreg = 3 | (nodeid <<4) | (linkn<<8);
+ /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
+ for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4);
+ if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
+ break;
+ }
+ }
+ if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/
+ /*update to 0xe0...*/
+ if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */
+ print_linkn_in("\tbusn=", next_busn);
+ tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
+ next_busn+=0x3f+1;
+
+#if CONFIG_K8_ALLOCATE_IO_RANGE == 1
+ /* io range allocation */
+ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
+ tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
+ pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
+ next_io_base += 0x3+0x1;
+#endif
+
+ }
+ }
+ /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
+
+ for(nodeid = 1; nodeid<nodes; nodeid++) {
+ int i;
+ u32 dev;
+ dev = PCI_BDF(0, 0x18+nodeid,1);
+ for(i = 0; i< 4; i++) {
+ unsigned regpos;
+ regpos = 0xe0 + i * 4;
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos);
+ pci_write_config32(dev, regpos, reg);
+ }
+
+#if CONFIG_K8_ALLOCATE_IO_RANGE == 1
+ /* io range allocation */
+ for(i = 0; i< 4; i++) {
+ unsigned regpos;
+ regpos = 0xc4 + i * 8;
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos);
+ pci_write_config32(dev, regpos, reg);
+ }
+ for(i = 0; i< 4; i++) {
+ unsigned regpos;
+ regpos = 0xc0 + i * 8;
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos);
+ pci_write_config32(dev, regpos, reg);
+ }
+#endif
+ }
+
+ /* recount ht_c_num*/
+ u8 i=0;
+ for(ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ reg = pci_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4);
+ if(((reg & 0xf) != 0x0)) {
+ i++;
+ }
+ }
+
+ sysinfo->ht_c_num = i;
+ ht_setup_chains(i, sysinfo);
+ sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
+
+}
+
+int optimize_link_incoherent_ht(struct sys_info *sysinfo)
+{
+ // We need to use recorded link pair info to optimize the link
+ int i;
+ int reset_needed = 0;
+
+ unsigned link_pair_num = sysinfo->link_pair_num;
+
+ for(i=0; i< link_pair_num; i++) {
+ struct link_pair_st *link_pair= &sysinfo->link_pair[i];
+ reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
+ }
+
+ reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
+
+ return reset_needed;
+
+}
+
+
+
Added: coreboot-v3/northbridge/amd/k8/northbridge.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/northbridge.c (rev 0)
+++ coreboot-v3/northbridge/amd/k8/northbridge.c 2008-08-11 23:55:10 UTC (rev 749)
@@ -0,0 +1,1360 @@
+/*
+ * K8 northbridge
+ * This file is part of the coreboot project.
+ * Copyright (C) 2004-2005 Linux Networx
+ * (Written by Eric Biederman <ebiederman at lnxi.com> and Jason Schildt for Linux Networx)
+ * Copyright (C) 2005-7 YingHai Lu
+ * Copyright (C) 2005 Ollie Lo
+ * Copyright (C) 2005-2007 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+/* This should be done by Eric
+ 2004.12 yhlu add dual core support
+ 2005.01 yhlu add support move apic before pci_domain in MB Config.lb
+ 2005.02 yhlu add e0 memory hole support
+ 2005.11 yhlu add put sb ht chain on bus 0
+*/
+
+#include <console.h>
+#include <lib.h>
+#include <string.h>
+#include <mtrr.h>
+#include <macros.h>
+#include <spd.h>
+#include <cpu.h>
+#include <msr.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
+#include <device/pci.h>
+#include <device/hypertransport_def.h>
+#include <device/hypertransport.h>
+#include <mc146818rtc.h>
+#include <lib.h>
+#include <lapic.h>
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+#include <cpu/amd/model_fxx_rev.h>
+#endif
+
+struct amdk8_sysconf sysconf;
+
+#define FX_DEVS 8
+static struct device * __f0_dev[FX_DEVS];
+static struct device * __f1_dev[FX_DEVS];
+
+#if 0
+static void debug_fx_devs(void)
+{
+ int i;
+ for(i = 0; i < FX_DEVS; i++) {
+ struct device * dev;
+ dev = __f0_dev[i];
+ if (dev) {
+ printk(BIOS_DEBUG, "__f0_dev[%d]: %s bus: %p\n",
+ i, dev_path(dev), dev->bus);
+ }
+ dev = __f1_dev[i];
+ if (dev) {
+ printk(BIOS_DEBUG, "__f1_dev[%d]: %s bus: %p\n",
+ i, dev_path(dev), dev->bus);
+ }
+ }
+}
+#endif
+
+static void get_fx_devs(void)
+{
+ int i;
+ if (__f1_dev[0]) {
+ return;
+ }
+ for(i = 0; i < FX_DEVS; i++) {
+ __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
+ __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
+ }
+ if (!__f1_dev[0]) {
+ die("Cannot find 0:0x18.1\n");
+ }
+}
+
+static u32 f1_read_config32(unsigned reg)
+{
+ get_fx_devs();
+ return pci_read_config32(__f1_dev[0], reg);
+}
+
+static void f1_write_config32(unsigned reg, u32 value)
+{
+ int i;
+ get_fx_devs();
+ for(i = 0; i < FX_DEVS; i++) {
+ struct device * dev;
+ dev = __f1_dev[i];
+ if (dev && dev->enabled) {
+ pci_write_config32(dev, reg, value);
+ }
+ }
+}
+
+static unsigned int amdk8_nodeid(struct device * dev)
+{
+ return (dev->path.pci.devfn >> 3) - 0x18;
+}
+
+static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
+{
+
+ u32 link_type;
+ int i;
+ u32 busses, config_busses;
+ unsigned free_reg, config_reg;
+ unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
+ unsigned max_bus;
+ unsigned min_bus;
+ unsigned max_devfn;
+
+ dev->link[link].cap = 0x80 + (link *0x20);
+ do {
+ link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
+ } while(link_type & ConnectionPending);
+ if (!(link_type & LinkConnected)) {
+ return max;
+ }
+ do {
+ link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
+ } while(!(link_type & InitComplete));
+ if (!(link_type & NonCoherent)) {
+ return max;
+ }
+ /* See if there is an available configuration space mapping
+ * register in function 1.
+ */
+ free_reg = 0;
+ for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
+ u32 config;
+ config = f1_read_config32(config_reg);
+ if (!free_reg && ((config & 3) == 0)) {
+ free_reg = config_reg;
+ continue;
+ }
+ if (((config & 3) == 3) &&
+ (((config >> 4) & 7) == nodeid) &&
+ (((config >> 8) & 3) == link)) {
+ break;
+ }
+ }
+ if (free_reg && (config_reg > 0xec)) {
+ config_reg = free_reg;
+ }
+ /* If we can't find an available configuration space mapping
+ * register skip this bus
+ */
+ if (config_reg > 0xec) {
+ return max;
+ }
+
+ /* Set up the primary, secondary and subordinate bus numbers.
+ * We have no idea how many busses are behind this bridge yet,
+ * so we set the subordinate bus number to 0xff for the moment.
+ */
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
+ // first chain will on bus 0
+ if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
+ min_bus = max;
+ }
+ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
+ // second chain will be on 0x40, third 0x80, forth 0xc0
+ else {
+ min_bus = ((max>>6) + 1) * 0x40;
+ }
+ max = min_bus;
+ #else
+ //other ...
+ else {
+ min_bus = ++max;
+ }
+ #endif
+#else
+ min_bus = ++max;
+#endif
+ max_bus = 0xff;
+
+ dev->link[link].secondary = min_bus;
+ dev->link[link].subordinate = max_bus;
+
+ /* Read the existing primary/secondary/subordinate bus
+ * number configuration.
+ */
+ busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
+ config_busses = f1_read_config32(config_reg);
+
+ /* Configure the bus numbers for this bridge: the configuration
+ * transactions will not be propagates by the bridge if it is
+ * not correctly configured
+ */
+ busses &= 0xff000000;
+ busses |= (((unsigned int)(dev->bus->secondary) << 0) |
+ ((unsigned int)(dev->link[link].secondary) << 8) |
+ ((unsigned int)(dev->link[link].subordinate) << 16));
+ pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
+
+ config_busses &= 0x000fc88;
+ config_busses |=
+ (3 << 0) | /* rw enable, no device compare */
+ (( nodeid & 7) << 4) |
+ (( link & 3 ) << 8) |
+ ((dev->link[link].secondary) << 16) |
+ ((dev->link[link].subordinate) << 24);
+ f1_write_config32(config_reg, config_busses);
+
+ /* Now we can scan all of the subordinate busses i.e. the
+ * chain on the hypertranport link
+ */
+ for(i=0;i<4;i++) {
+ ht_unitid_base[i] = 0x20;
+ }
+
+ if (min_bus == 0)
+ max_devfn = (0x17<<3) | 7;
+ else
+ max_devfn = (0x1f<<3) | 7;
+
+ max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
+
+ /* We know the number of busses behind this bridge. Set the
+ * subordinate bus number to it's real value
+ */
+ dev->link[link].subordinate = max;
+ busses = (busses & 0xff00ffff) |
+ ((unsigned int) (dev->link[link].subordinate) << 16);
+ pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
+
+ config_busses = (config_busses & 0x00ffffff) |
+ (dev->link[link].subordinate << 24);
+ f1_write_config32(config_reg, config_busses);
+
+ {
+ // config config_reg, and ht_unitid_base to update hcdn_reg;
+ int index;
+ unsigned temp = 0;
+ index = (config_reg-0xe0) >> 2;
+ for(i=0;i<4;i++) {
+ temp |= (ht_unitid_base[i] & 0xff) << (i*8);
+ }
+
+ sysconf.hcdn_reg[index] = temp;
+
+ }
+
+ return max;
+}
+
+static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max)
+{
+ unsigned nodeid;
+ unsigned link;
+ unsigned sblink = 0;
+ unsigned offset_unitid = 0;
+ nodeid = amdk8_nodeid(dev);
+
+ if(nodeid==0) {
+ sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ offset_unitid = 1;
+ #endif
+ // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2,
+ // but put 8151 on link0
+ max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid );
+#endif
+ }
+
+ for(link = 0; link < dev->links; link++) {
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
+ if( (nodeid == 0) && (sblink == link) ) continue; //already done
+#endif
+ offset_unitid = 0;
+ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ if((nodeid == 0) && (sblink == link))
+ #endif
+ offset_unitid = 1;
+ #endif
+
+ max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
+ }
+
+ return max;
+}
+
+
+static int reg_useable(unsigned reg,
+ struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link)
+{
+ struct resource *res;
+ unsigned nodeid, link;
+ int result;
+ res = 0;
+ for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
+ struct device * dev;
+ dev = __f0_dev[nodeid];
+ for(link = 0; !res && (link < 3); link++) {
+ res = probe_resource(dev, 0x100 + (reg | link));
+ }
+ }
+ result = 2;
+ if (res) {
+ result = 0;
+ if ( (goal_link == (link - 1)) &&
+ (goal_nodeid == (nodeid - 1)) &&
+ (res->flags <= 1)) {
+ result = 1;
+ }
+ }
+
+ return result;
+}
+
+static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link)
+{
+ struct resource *resource;
+ unsigned free_reg, reg;
+ resource = 0;
+ free_reg = 0;
+ for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+ int result;
+ result = reg_useable(reg, dev, nodeid, link);
+ if (result == 1) {
+ /* I have been allocated this one */
+ break;
+ }
+ else if (result > 1) {
+ /* I have a free register pair */
+ free_reg = reg;
+ }
+ }
+ if (reg > 0xd8) {
+ reg = free_reg;
+ }
+ if (reg > 0) {
+ resource = new_resource(dev, 0x100 + (reg | link));
+ }
+ return resource;
+}
+
+static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link)
+{
+ struct resource *resource;
+ unsigned free_reg, reg;
+ resource = 0;
+ free_reg = 0;
+ for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
+ int result;
+ result = reg_useable(reg, dev, nodeid, link);
+ if (result == 1) {
+ /* I have been allocated this one */
+ break;
+ }
+ else if (result > 1) {
+ /* I have a free register pair */
+ free_reg = reg;
+ }
+ }
+ if (reg > 0xb8) {
+ reg = free_reg;
+ }
+ if (reg > 0) {
+ resource = new_resource(dev, 0x100 + (reg | link));
+ }
+ return resource;
+}
+
+static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link)
+{
+ struct resource *resource;
+
+ /* Initialize the io space constraints on the current bus */
+ resource = amdk8_find_iopair(dev, nodeid, link);
+ if (resource) {
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = log2(HT_IO_HOST_ALIGN);
+ resource->gran = log2(HT_IO_HOST_ALIGN);
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO;
+ compute_allocate_resource(&dev->link[link], resource,
+ IORESOURCE_IO, IORESOURCE_IO);
+ }
+
+ /* Initialize the prefetchable memory constraints on the current bus */
+ resource = amdk8_find_mempair(dev, nodeid, link);
+ if (resource) {
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->limit = 0xffffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ compute_allocate_resource(&dev->link[link], resource,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH);
+ }
+
+ /* Initialize the memory constraints on the current bus */
+ resource = amdk8_find_mempair(dev, nodeid, link);
+ if (resource) {
+ resource->base = 0;
+ resource->size = 0;
+ resource->align = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->limit = 0xffffffffffULL;
+ resource->flags = IORESOURCE_MEM;
+ compute_allocate_resource(&dev->link[link], resource,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ IORESOURCE_MEM);
+ }
+}
+
+static void amdk8_read_resources(struct device * dev)
+{
+ unsigned nodeid, link;
+ nodeid = amdk8_nodeid(dev);
+ for(link = 0; link < dev->links; link++) {
+ if (dev->link[link].children) {
+ amdk8_link_read_bases(dev, nodeid, link);
+ }
+ }
+}
+
+static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid)
+{
+ resource_t rbase, rend;
+ unsigned reg, link;
+ char buf[50];
+
+ /* Make certain the resource has actually been set */
+ if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+ return;
+ }
+
+ /* If I have already stored this resource don't worry about it */
+ if (resource->flags & IORESOURCE_STORED) {
+ return;
+ }
+
+ /* Only handle PCI memory and IO resources */
+ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+ return;
+
+ /* Ensure I am actually looking at a resource of function 1 */
+ if (resource->index < 0x100) {
+ return;
+ }
+ /* Get the base address */
+ rbase = resource->base;
+
+ /* Get the limit (rounded up) */
+ rend = resource_end(resource);
+
+ /* Get the register and link */
+ reg = resource->index & 0xfc;
+ link = resource->index & 3;
+
+ if (resource->flags & IORESOURCE_IO) {
+ u32 base, limit;
+ compute_allocate_resource(&dev->link[link], resource,
+ IORESOURCE_IO, IORESOURCE_IO);
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x4);
+ base &= 0xfe000fcc;
+ base |= rbase & 0x01fff000;
+ base |= 3;
+ limit &= 0xfe000fc8;
+ limit |= rend & 0x01fff000;
+ limit |= (link & 3) << 4;
+ limit |= (nodeid & 7);
+
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n",
+ __func__, dev_path(dev), link);
+ base |= PCI_IO_BASE_VGA_EN;
+ }
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+ base |= PCI_IO_BASE_NO_ISA;
+ }
+
+ f1_write_config32(reg + 0x4, limit);
+ f1_write_config32(reg, base);
+ }
+ else if (resource->flags & IORESOURCE_MEM) {
+ u32 base, limit;
+ compute_allocate_resource(&dev->link[link], resource,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x4);
+ base &= 0x000000f0;
+ base |= (rbase >> 8) & 0xffffff00;
+ base |= 3;
+ limit &= 0x00000048;
+ limit |= (rend >> 8) & 0xffffff00;
+ limit |= (link & 3) << 4;
+ limit |= (nodeid & 7);
+ f1_write_config32(reg + 0x4, limit);
+ f1_write_config32(reg, base);
+ }
+ resource->flags |= IORESOURCE_STORED;
+ sprintf(buf, " <node %d link %d>",
+ nodeid, link);
+ report_resource_stored(dev, resource, buf);
+}
+
+/**
+ *
+ * I tried to reuse the resource allocation code in amdk8_set_resource()
+ * but it is too diffcult to deal with the resource allocation magic.
+ */
+#if CONFIG_MULTIPLE_VGA_INIT == 1
+extern struct device * vga_pri; // the primary vga device, defined in device.c
+#endif
+
+static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid)
+{
+ struct resource *resource;
+ unsigned link;
+ u32 base, limit;
+ unsigned reg;
+
+ /* find out which link the VGA card is connected,
+ * we only deal with the 'first' vga card */
+ for (link = 0; link < dev->links; link++) {
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+#if CONFIG_MULTIPLE_VGA_INIT == 1
+ printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+ dev->link[link].secondary,dev->link[link].subordinate);
+ /* We need to make sure the vga_pri is under the link */
+ if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
+ (vga_pri->bus->secondary <= dev->link[link].subordinate )
+ )
+#endif
+ break;
+ }
+ }
+
+ /* no VGA card installed */
+ if (link == dev->links)
+ return;
+
+ printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+
+ /* allocate a temp resrouce for legacy VGA buffer */
+ resource = amdk8_find_mempair(dev, nodeid, link);
+ if(!resource){
+ printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n");
+ return;
+ }
+ resource->base = 0xa0000;
+ resource->size = 0x20000;
+
+ /* write the resource to the hardware */
+ reg = resource->index & 0xfc;
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x4);
+ base &= 0x000000f0;
+ base |= (resource->base >> 8) & 0xffffff00;
+ base |= 3;
+ limit &= 0x00000048;
+ limit |= (resource_end(resource) >> 8) & 0xffffff00;
+ limit |= (resource->index & 3) << 4;
+ limit |= (nodeid & 7);
+ f1_write_config32(reg + 0x4, limit);
+ f1_write_config32(reg, base);
+
+ /* release the temp resource */
+ resource->flags = 0;
+}
+
+static void amdk8_set_resources(struct device * dev)
+{
+ unsigned nodeid, link;
+ int i;
+
+ /* Find the nodeid */
+ nodeid = amdk8_nodeid(dev);
+
+ amdk8_create_vga_resource(dev, nodeid);
+
+ /* Set each resource we have found */
+ for(i = 0; i < dev->resources; i++) {
+ amdk8_set_resource(dev, &dev->resource[i], nodeid);
+ }
+
+ for(link = 0; link < dev->links; link++) {
+ struct bus *bus;
+ bus = &dev->link[link];
+ if (bus->children) {
+ assign_resources(bus);
+ }
+ }
+}
+
+static void amdk8_enable_resources(struct device * dev)
+{
+ pci_dev_enable_resources(dev);
+ enable_childrens_resources(dev);
+}
+
+static void mcf0_control_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. Nothing to do ...");
+
+ printk(BIOS_DEBUG, "done.\n");
+}
+
+
+static void k8_pci_domain_read_resources(struct device * dev)
+{
+ struct resource *resource;
+ unsigned reg;
+
+ /* Find the already assigned resource pairs */
+ get_fx_devs();
+ for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
+ u32 base, limit;
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x04);
+ /* Is this register allocated? */
+ if ((base & 3) != 0) {
+ unsigned nodeid, link;
+ struct device * dev;
+ nodeid = limit & 7;
+ link = (limit >> 4) & 3;
+ dev = __f0_dev[nodeid];
+ if (dev) {
+ /* Reserve the resource */
+ struct resource *resource;
+ resource = new_resource(dev, 0x100 + (reg | link));
+ if (resource) {
+ resource->flags = 1;
+ }
+ }
+ }
+ }
+#if CONFIG_PCI_64BIT_PREF_MEM == 0
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ resource->base = 0x400;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ resource->limit = 0xfcffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+#else
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, 0);
+ resource->base = 0x400;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO;
+ compute_allocate_resource(&dev->link[0], resource,
+ IORESOURCE_IO, IORESOURCE_IO);
+
+ /* Initialize the system wide prefetchable memory resources constraints */
+ resource = new_resource(dev, 1);
+ resource->limit = 0xfcffffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ compute_allocate_resource(&dev->link[0], resource,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH);
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, 2);
+ resource->limit = 0xfcffffffffULL;
+ resource->flags = IORESOURCE_MEM;
+ compute_allocate_resource(&dev->link[0], resource,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ IORESOURCE_MEM);
+#endif
+}
+
+static void k8_ram_resource(struct device * dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *resource;
+
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+ struct resource **best_p = gp;
+ struct resource *best;
+ best = *best_p;
+ if (!best || (best->base > new->base)) {
+ best = new;
+ }
+ *best_p = best;
+}
+
+static u32 find_pci_tolm(struct bus *bus)
+{
+ struct resource *min;
+ u32 tolm;
+ min = 0;
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ tolm = 0xffffffffUL;
+ if (min && tolm > min->base) {
+ tolm = min->base;
+ }
+ return tolm;
+}
+
+#ifdef CONFIG_PCI_64BIT_PREF_MEM
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
+#endif
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+
+struct hw_mem_hole_info {
+ unsigned hole_startk;
+ int node_id;
+};
+
+static struct hw_mem_hole_info get_hw_mem_hole_info(void)
+{
+ struct hw_mem_hole_info mem_hole;
+ int i;
+
+ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+ mem_hole.node_id = -1;
+
+ for (i = 0; i < 8; i++) {
+ u32 base;
+ u32 hole;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+
+ hole = pci_read_config32(__f1_dev[i], 0xf0);
+ if(hole & 1) { // we find the hole
+ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+ mem_hole.node_id = i; // record the node No with hole
+ break; // only one hole
+ }
+ }
+
+ //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
+ if(mem_hole.node_id==-1) {
+ u32 limitk_pri = 0;
+ for(i=0; i<8; i++) {
+ u32 base, limit;
+ unsigned base_k, limit_k;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+
+ base_k = (base & 0xffff0000) >> 2;
+ if(limitk_pri != base_k) { // we find the hole
+ mem_hole.hole_startk = limitk_pri;
+ mem_hole.node_id = i;
+ break; //only one hole
+ }
+
+ limit = f1_read_config32(0x44 + (i << 3));
+ limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
+ limitk_pri = limit_k;
+ }
+ }
+
+ return mem_hole;
+
+}
+static void disable_hoist_memory(unsigned long hole_startk, int i)
+{
+ int ii;
+ struct device * dev;
+ u32 base, limit;
+ u32 hoist;
+ u32 hole_sizek;
+
+
+ //1. find which node has hole
+ //2. change limit in that node.
+ //3. change base and limit in later node
+ //4. clear that node f0
+
+ //if there is not mem hole enabled, we need to change it's base instead
+
+ hole_sizek = (4*1024*1024) - hole_startk;
+
+ for(ii=7;ii>i;ii--) {
+
+ base = f1_read_config32(0x40 + (ii << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+ limit = f1_read_config32(0x44 + (ii << 3));
+ f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
+ f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+ }
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+ dev = __f1_dev[i];
+ hoist = pci_read_config32(dev, 0xf0);
+ if(hoist & 1) {
+ pci_write_config32(dev, 0xf0, 0);
+ }
+ else {
+ base = pci_read_config32(dev, 0x40 + (i << 3));
+ f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
+ }
+
+}
+
+static u32 hoist_memory(unsigned long hole_startk, int i)
+{
+ int ii;
+ u32 carry_over;
+ struct device * dev;
+ u32 base, limit;
+ u32 basek;
+ u32 hoist;
+
+ carry_over = (4*1024*1024) - hole_startk;
+
+ for(ii=7;ii>i;ii--) {
+
+ base = f1_read_config32(0x40 + (ii << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+ limit = f1_read_config32(0x44 + (ii << 3));
+ f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
+ f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
+ }
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+ dev = __f1_dev[i];
+ base = pci_read_config32(dev, 0x40 + (i << 3));
+ basek = (base & 0xffff0000) >> 2;
+ if(basek == hole_startk) {
+ //don't need set memhole here, because hole off set will be 0, overflow
+ //so need to change base reg instead, new basek will be 4*1024*1024
+ base &= 0x0000ffff;
+ base |= (4*1024*1024)<<2;
+ f1_write_config32(0x40 + (i<<3), base);
+ }
+ else
+ {
+ hoist = /* hole start address */
+ ((hole_startk << 10) & 0xff000000) +
+ /* hole address to memory controller address */
+ (((basek + carry_over) >> 6) & 0x0000ff00) +
+ /* enable */
+ 1;
+
+ pci_write_config32(dev, 0xf0, hoist);
+ }
+
+ return carry_over;
+}
+#endif
+
+static void k8_pci_domain_set_resources(struct device * dev)
+{
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+ struct resource *io, *mem1, *mem2;
+ struct resource *resource, *last;
+#endif
+ unsigned long mmio_basek;
+ u32 pci_tolm;
+ int i, idx;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ struct hw_mem_hole_info mem_hole;
+ unsigned reset_memhole = 1;
+#endif
+
+#if 0
+ /* Place the IO devices somewhere safe */
+ io = find_resource(dev, 0);
+ io->base = DEVICE_IO_START;
+#endif
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+ /* Now reallocate the pci resources memory with the
+ * highest addresses I can manage.
+ */
+ mem1 = find_resource(dev, 1);
+ mem2 = find_resource(dev, 2);
+
+#if 1
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
+#endif
+
+ /* See if both resources have roughly the same limits */
+ if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+ ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+ {
+ /* If so place the one with the most stringent alignment first
+ */
+ if (mem2->align > mem1->align) {
+ struct resource *tmp;
+ tmp = mem1;
+ mem1 = mem2;
+ mem2 = tmp;
+ }
+ /* Now place the memory as high up as it will go */
+ mem2->base = resource_max(mem2);
+ mem1->limit = mem2->base - 1;
+ mem1->base = resource_max(mem1);
+ }
+ else {
+ /* Place the resources as high up as they will go */
+ mem2->base = resource_max(mem2);
+ mem1->base = resource_max(mem1);
+ }
+
+#if 1
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
+#endif
+
+ last = &dev->resource[dev->resources];
+ for(resource = &dev->resource[0]; resource < last; resource++)
+ {
+#if 1
+ resource->flags |= IORESOURCE_ASSIGNED;
+ resource->flags &= ~IORESOURCE_STORED;
+#endif
+ compute_allocate_resource(&dev->link[0], resource,
+ BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
+
+ resource->flags |= IORESOURCE_STORED;
+ report_resource_stored(dev, resource, "");
+
+ }
+#endif
+
+
+ pci_tolm = find_pci_tolm(&dev->link[0]);
+
+#warning "FIXME handle interleaved nodes"
+ mmio_basek = pci_tolm >> 10;
+ /* Round mmio_basek to something the processor can support */
+ mmio_basek &= ~((1 << 6) -1);
+
+#if 1
+#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
+ /* Round the mmio hold to 64M */
+ mmio_basek &= ~((64*1024) - 1);
+#endif
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
+ * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
+ * otherwise We reset the hole to the mmio_basek
+ */
+ #ifndef CONFIG_K8_REV_F_SUPPORT
+ if (!is_cpu_pre_e0()) {
+ #endif
+
+ mem_hole = get_hw_mem_hole_info();
+
+ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
+ mmio_basek = mem_hole.hole_startk;
+ reset_memhole = 0;
+ }
+
+ //mmio_basek = 3*1024*1024; // for debug to meet boundary
+
+ if(reset_memhole) {
+ if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
+ // We need to reset our Mem Hole, because We want more big HOLE than we already set
+ //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
+ disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
+ }
+
+ #if HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
+ u32 basek_pri;
+ for (i = 0; i < 8; i++) {
+ u32 base;
+ u32 basek;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+
+ basek = (base & 0xffff0000) >> 2;
+ if(mmio_basek == basek) {
+ mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
+ break;
+ }
+ basek_pri = basek;
+ }
+ #endif
+ }
+
+#ifndef CONFIG_K8_REV_F_SUPPORT
+ } // is_cpu_pre_e0
+#endif
+
+#endif
+
+ idx = 0x10;
+ for(i = 0; i < 8; i++) {
+ u32 base, limit;
+ unsigned basek, limitk, sizek;
+ base = f1_read_config32(0x40 + (i << 3));
+ limit = f1_read_config32(0x44 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+ basek = (base & 0xffff0000) >> 2;
+ limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
+ sizek = limitk - basek;
+
+ /* see if we need a hole from 0xa0000 to 0xbffff */
+ if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
+ k8_ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
+ idx += 0x10;
+ basek = (8*64)+(16*16);
+ sizek = limitk - ((8*64)+(16*16));
+
+ }
+
+
+ printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+
+ /* See if I need to split the region to accomodate pci memory space */
+ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+ if (basek <= mmio_basek) {
+ unsigned pre_sizek;
+ pre_sizek = mmio_basek - basek;
+ if(pre_sizek>0) {
+ k8_ram_resource(dev, (idx | i), basek, pre_sizek);
+ idx += 0x10;
+ sizek -= pre_sizek;
+ }
+ #if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ if(reset_memhole)
+ #ifndef CONFIG_K8_REV_F_SUPPORT
+ if(!is_cpu_pre_e0() )
+ #endif
+ sizek += hoist_memory(mmio_basek,i);
+ #endif
+
+ basek = mmio_basek;
+ }
+ if ((basek + sizek) <= 4*1024*1024) {
+ sizek = 0;
+ }
+ else {
+ basek = 4*1024*1024;
+ sizek -= (4*1024*1024 - mmio_basek);
+ }
+ }
+ k8_ram_resource(dev, (idx | i), basek, sizek);
+ idx += 0x10;
+ }
+ assign_resources(&dev->link[0]);
+}
+
+static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
+{
+ unsigned reg;
+ int i;
+ /* Unmap all of the HT chains */
+ for(reg = 0xe0; reg <= 0xec; reg += 4) {
+ f1_write_config32(reg, 0);
+ }
+ max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
+
+ /* Tune the hypertransport transaction for best performance.
+ * Including enabling relaxed ordering if it is safe.
+ */
+ get_fx_devs();
+ for(i = 0; i < FX_DEVS; i++) {
+ struct device * f0_dev;
+ f0_dev = __f0_dev[i];
+ if (f0_dev && f0_dev->enabled) {
+ u32 httc;
+ httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
+ httc &= ~HTTC_RSP_PASS_PW;
+ if (!dev->link[0].disable_relaxed_ordering) {
+ httc |= HTTC_RSP_PASS_PW;
+ }
+ printk(BIOS_SPEW, "%s passpw: %s\n",
+ dev_path(dev),
+ (!dev->link[0].disable_relaxed_ordering)?
+ "enabled":"disabled");
+ pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
+ }
+ }
+ return max;
+}
+
+
+static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
+{
+ struct bus *cpu_bus;
+ struct device * dev_mc;
+ int bsp_apicid;
+ int i,j;
+ unsigned nb_cfg_54;
+ unsigned siblings;
+ int e0_later_single_core;
+ int disable_siblings;
+
+ nb_cfg_54 = 0;
+ sysconf.enabled_apic_ext_id = 0;
+ sysconf.lift_bsp_apicid = 0;
+ siblings = 0;
+
+ /* Find the bootstrap processors apicid */
+ bsp_apicid = lapicid();
+ sysconf.apicid_offset = bsp_apicid;
+
+ disable_siblings = !CONFIG_LOGICAL_CPUS;
+#if CONFIG_LOGICAL_CPUS == 1
+ get_option(&disable_siblings, "dual_core");
+#endif
+
+ // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
+ // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
+
+ nb_cfg_54 = read_nb_cfg_54();
+
+ dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ if (!dev_mc) {
+ die("0:18.0 not found?");
+ }
+
+ sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
+
+
+ if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
+ {
+ sysconf.enabled_apic_ext_id = 1;
+ if(bsp_apicid == 0) {
+ /* bsp apic id is not changed */
+ sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
+ } else
+ {
+ sysconf.lift_bsp_apicid = 1;
+ }
+
+ }
+
+ /* Find which cpus are present */
+ cpu_bus = &dev->link[0];
+ for(i = 0; i < sysconf.nodes; i++) {
+ struct device * dev, *cpu;
+ struct device_path cpu_path;
+
+ /* Find the cpu's pci device */
+ dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+ if (!dev) {
+ /* If I am probing things in a weird order
+ * ensure all of the cpu's pci devices are found.
+ */
+ int j;
+ struct device * dev_f0;
+ for(j = 0; j <= 3; j++) {
+ dev = pci_probe_dev(NULL, dev_mc->bus,
+ PCI_DEVFN(0x18 + i, j));
+ }
+ /* Ok, We need to set the links for that device.
+ * otherwise the device under it will not be scanned
+ */
+ dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
+ if(dev_f0) {
+ dev_f0->links = 3;
+ for(j=0;j<3;j++) {
+ dev_f0->link[j].link = j;
+ dev_f0->link[j].dev = dev_f0;
+ }
+ }
+
+ }
+
+ e0_later_single_core = 0;
+ if (dev && dev->enabled) {
+ j = pci_read_config32(dev, 0xe8);
+ j = (j >> 12) & 3; // dev is func 3
+ printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), j);
+
+ if(nb_cfg_54) {
+ // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
+ // ----> you can mixed single core e0 and dual core e0 at any sequence
+ // That is the typical case
+
+ if(j == 0 ){
+ #ifndef CONFIG_K8_REV_F_SUPPORT
+ e0_later_single_core = is_e0_later_in_bsp(i); // single core
+ #else
+ e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
+ #endif
+ } else {
+ e0_later_single_core = 0;
+ }
+ if(e0_later_single_core) {
+ printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
+
+ j=1;
+ }
+
+ if(siblings > j ) {
+ }
+ else {
+ siblings = j;
+ }
+ } else {
+ siblings = j;
+ }
+ }
+
+ unsigned jj;
+ if(e0_later_single_core || disable_siblings) {
+ jj = 0;
+ } else
+ {
+ jj = siblings;
+ }
+#if 0
+ jj = 0; // if create cpu core1 path in amd_siblings by core0
+#endif
+
+ for (j = 0; j <=jj; j++ ) {
+
+ /* Build the cpu device path */
+ cpu_path.type = DEVICE_PATH_APIC;
+ cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
+
+ /* See if I can find the cpu */
+ cpu = find_dev_path(cpu_bus, &cpu_path);
+
+ /* Enable the cpu if I have the processor */
+ if (dev && dev->enabled) {
+ /* this is a CPU */
+ struct device_id did;
+ did.type = DEVICE_ID_CPU;
+#warning fill cpuid; right now it is zero
+ if (!cpu) {
+ cpu = alloc_dev(cpu_bus, &cpu_path, &did);
+ }
+ if (cpu) {
+ cpu->enabled = 1;
+ }
+ }
+
+ /* Disable the cpu if I don't have the processor */
+ if (cpu && (!dev || !dev->enabled)) {
+ cpu->enabled = 0;
+ }
+
+ /* Report what I have done */
+ if (cpu) {
+ cpu->path.apic.node_id = i;
+ cpu->path.apic.core_id = j;
+ if(sysconf.enabled_apic_ext_id) {
+ if(sysconf.lift_bsp_apicid) {
+ cpu->path.apic.apic_id += sysconf.apicid_offset;
+ } else
+ {
+ if (cpu->path.apic.apic_id != 0)
+ cpu->path.apic.apic_id += sysconf.apicid_offset;
+ }
+ }
+ printk(BIOS_DEBUG, "CPU: %s %s\n",
+ dev_path(cpu), cpu->enabled?"enabled":"disabled");
+ }
+
+ } //j
+ }
+ return max;
+}
+
+static void cpu_bus_init(struct device * dev)
+{
+ /* unclear if we need this any more. CPUs are in the device tree. */
+ // initialize_cpus(&dev->link[0]);
+ //so what do we do? This is a first for v3.
+}
+
+static void cpu_bus_noop(struct device * dev)
+{
+}
+
+struct device_operations k8_ops = {
+ .id = {.type = DEVICE_ID_PCI,
+ {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x1100}}},
+ .constructor = default_device_constructor,
+ .reset_bus = pci_bus_reset,
+ .phase3_scan = amdk8_scan_chains,
+ .phase4_read_resources = amdk8_read_resources,
+ .phase4_set_resources = amdk8_set_resources,
+ .phase5_enable_resources = amdk8_enable_resources,
+ .phase6_init = mcf0_control_init,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+
+
+/* arguably, this should no longer be here. It was part of a nasty kludge because the CPUs
+ * were never really part of the device tree. The solution crafted in v2 was expedient but
+ * hardly comprehensible. It may be removed soon.
+ */
+/* the interesting question, of course: should we really be going for an *exact* match? Or a range? */
+struct device_operations k8cpu_ops = {
+ .id = {.type = DEVICE_ID_CPU,
+ {.cpu = {"Genuine AMD"}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = cpu_bus_scan,
+ .phase4_read_resources = cpu_bus_noop,
+ .phase4_set_resources = cpu_bus_noop,
+ .phase5_enable_resources = cpu_bus_noop,
+ .phase6_init = cpu_bus_init,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+struct device_operations k8apic_ops = {
+ .id = {.type = DEVICE_ID_APIC_CLUSTER,
+ {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x1100}}},
+ .constructor = default_device_constructor,
+ .phase3_scan = k8_domain_scan_bus,
+ .phase4_read_resources = k8_pci_domain_read_resources,
+ .phase4_set_resources = k8_pci_domain_set_resources,
+ .phase5_enable_resources = enable_childrens_resources,
+ .ops_pci = &pci_dev_ops_pci,
+ .ops_pci_bus = &pci_cf8_conf1,
+};
Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-11 23:19:53 UTC (rev 748)
+++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-11 23:55:10 UTC (rev 749)
@@ -595,7 +595,7 @@
int value, low;
/* no memset per now and we might want non-zero values */
sz.per_rank = 0;
- sz.side1;
+ sz.side1 = 0;
sz.side2 = 0;
sz.rows = 0;
sz.col = 0;
More information about the coreboot
mailing list