[coreboot] r848 - in coreboot-v3: arch/x86 mainboard/amd/serengeti

[svn at coreboot.org]

Author: rminnich
Date: 2008-08-30 05:42:01 +0200 (Sat, 30 Aug 2008)
New Revision: 848

Modified:
   coreboot-v3/arch/x86/stage1_mtrr.c
   coreboot-v3/mainboard/amd/serengeti/Makefile
Log:
One typo and one change to get our bootblock back into 20k.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/stage1_mtrr.c
===================================================================
--- coreboot-v3/arch/x86/stage1_mtrr.c	2008-08-30 03:35:40 UTC (rev 847)
+++ coreboot-v3/arch/x86/stage1_mtrr.c	2008-08-30 03:42:01 UTC (rev 848)
@@ -63,7 +63,7 @@
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
-	set_var_mtrr(0, 0x00000000, COREBOOT_MEM_TOPK << 10, type);
+	set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
 	enable_cache();
 }
 

Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile	2008-08-30 03:35:40 UTC (rev 847)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile	2008-08-30 03:42:01 UTC (rev 848)
@@ -27,13 +27,13 @@
 			$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
 			$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
 			$(src)/northbridge/amd/k8/coherent_ht.c \
-			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
+			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \