[coreboot] HT reset hang on 690G/SB600 board Asus M2A-VM
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Thu Dec 11 04:42:33 CET 2008
Hi Joe,
thanks for your patch. I have tried it, but the machine still hangs
after HT reset.
Regards,
Carl-Daniel
On 11.12.2008 03:42, Bao, Zheng wrote:
> Hi,
> I doubt if the fid/vid code causes this problem. You can try to remove
> the
> Fid/vid code and see if the problem still exists.
>
> --- cache_as_ram_auto.c (revision 3789)
> +++ cache_as_ram_auto.c (working copy)
> @@ -197,17 +197,7 @@
> rs690_early_setup();
> sb600_early_setup();
>
> - msr=rdmsr(0xc0010042);
> - printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
> msr.lo);
> -
> - enable_fid_change();
> - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
> - init_fidvid_bsp(bsp_apicid);
>
> - /* show final fid and vid */
> - msr=rdmsr(0xc0010042);
> - printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi,
> msr.lo);
>
> needs_reset = optimize_link_coherent_ht();
> needs_reset |= optimize_link_incoherent_ht(sysinfo);
> printk_debug("needs_reset=0x%x\n", needs_reset);
>
>
> Joe
> -----Original Message-----
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Carl-Daniel
> Hailfinger
> Sent: Thursday, December 11, 2008 10:04 AM
> To: Coreboot
> Subject: [coreboot] HT reset hang on 690G/SB600 board Asus M2A-VM
>
> Hi!
>
> I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very
> similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F
> SuperIO.
>
> My codebase is a slightly modified amd/dbm690t target. I only changed
> the CPU socket to AM2.
>
> coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting...
> bsp_apicid=0x0
> core0 started:
> SBLink=00
> NC node|link=00
> rs690_early_setup()
> get_cpu_rev EAX=0x50ff2.
> CPU Rev is K8_G0.
> NB Revision is A12.
> rs690_ht_init k8_ht_freq=0.
> k8_optimization()
> rs690_por_init
> sb600_early_setup()
> sb600_devices_por_init()
> sb600_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is 0x13
> sb600_devices_por_init(): IDE Device, BDF:0-20-1
> sb600_devices_por_init(): LPC Device, BDF:0-20-3
> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb600_devices_por_init(): SATA Device, BDF:0-18-0
> sb600_pmio_por_init()
> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202
> Current fid_cur: 0x2, fid_max: 0xa
> Requested fid_new: 0xa
> FidVid table step fidvid: 0xa
> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a
> needs_reset=0x1
> ht reset -
>
> It hangs after that soft reset. No POST code, nothing else.
>
> Any insights are appreciated.
>
> Processor info follows:
> hilbert:~ # cat /proc/cpuinfo
> processor : 0
> vendor_id : AuthenticAMD
> cpu family : 15
> model : 95
> model name : AMD Athlon(tm) 64 Processor 3000+
> stepping : 2
> cpu MHz : 1800.000
> cache size : 512 KB
> fpu : yes
> fpu_exception : yes
> cpuid level : 1
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt
> rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm svm extapic
> cr8_legacy
> bogomips : 3602.72
> TLB size : 1024 4K pages
> clflush size : 64
> cache_alignment : 64
> address sizes : 40 bits physical, 48 bits virtual
> power management: ts fid vid ttp tm stc
>
>
> Regards,
> Carl-Daniel
>
>
--
http://www.hailfinger.org/
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