[coreboot] ACPI S3 with coreboot-v2 on DBM690T

[Marc Jones]

Libo,

Good to see that you are making some progress.


On Thu, Dec 11, 2008 at 2:50 AM, Feng, Libo <Libo.Feng at amd.com> wrote:
...

> 1. Is it really necessary for CAR to move the stack from 0xc8000 in cache
> into 0x1f8000 in RAM at the final stage of CAR? Now that the stack works
> well in cache, why does CAR move the stack into RAM? For verifying RAM or
> other stuff?
>

The stack needs to be moved so that cache and memory can be mapped
normally in the main coreboot code.

> 2. When resuming from S3, I initialize RAM again instead of exiting
> self-Refresh. Lucky enough, RAM content is also kept intact in this way. I
> will try the exiting self-refresh later.
>
> My first attempt is to jump into the waking vector in the function of
> post_cache_as_ram, at this moment, RAM is accessible, I can get the waking
> vector. However, many devices are not initialized, the system is very
> unstable, I got different trace every time, the best was as below. So, after
> stuck a couple of days, I gave up and followed Rodulf's way as above.

A different trace may indicate memory is not a stable as you thought.
You really need to do the existing self refresh code. It should not be
difficult.

Marc