[coreboot] More v3 questions/issues

[Corey Osgood]

On Wed, Dec 17, 2008 at 6:51 PM, Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2006 at gmx.net> wrote:

> On 17.12.2008 22:19, Corey Osgood wrote:
> > On Wed, Dec 17, 2008 at 3:24 PM, Corey Osgood <corey.osgood at gmail.com
> >wrote:
> >
> >
> >> On Wed, Dec 17, 2008 at 2:03 PM, Myles Watson <mylesgw at gmail.com>
> wrote:
> >>
> >>
> >>> On Wed, Dec 17, 2008 at 11:43 AM, Corey Osgood <corey.osgood at gmail.com
> >wrote:
> >>>
> >>>
> >>>> On Tue, Dec 16, 2008 at 12:35 PM, Myles Watson <mylesgw at gmail.com
> >wrote:
> >>>>
> >>>>
> >>>>> Corey,
> >>>>>
> >>>>> I've been looking through the v2 code, but I don't see anywhere that
> pci
> >>>>> config reads/writes are enabled before scanning.  If you're
> interested, you
> >>>>> could send me a v2 boot log and I'll try to help more. You could also
> try
> >>>>> doing a direct pci config read to the device to see if it works
> before the
> >>>>> hang.
> >>>>>
> >>>> I got looking at some other drivers and reading some other mails on
> the
> >>>> list, and changing pci_ops to use cf0/cf8 fixed it, and also fixed my
> >>>> problems with the ide and sata drivers hanging (so all those phase3
> >>>> functions are back in phase6 where they belong). The system now boots
> to
> >>>> memtest and actually sees the memory to test now, but I'm still having
> a
> >>>> problem building the cpu driver, which means booting is EXTREMEMLY
> slow. The
> >>>> stage2 driver is in via/c7.c, but no matter where I try to include it
> in the
> >>>> make files, arch/x86/Makefile or mainboard/jetway/j7f2/Makefile, I get
> this
> >>>> error:
> >>>>
> >>>> make: *** No rule to make target
> >>>>
> `/home/corey/coreboot/coreboot-v3/build/mainboard/jetway/j7f2//home/corey/coreboot/coreboot-v3/arch/x86/via/c7.o',
> >>>> needed by `/home/corey/coreboot/coreboot-v3/build/coreboot.stage2'.
>  Stop.
> >>>>
> >>>> I'm no expert on makefiles, so I could use a hand. I've tried to
> locate
> >>>> where/how geodelx/cpu.c is built, but it doesn't seem that it ever is,
> >>>> adding a #error to the file still lets alix1c and other geodelx boards
> build
> >>>> without error.
> >>>>
> >>>> Other then that, things are looking VERY promising, I'm finishing up a
> >>>> few things I put off before, and once the CPU driver is running I'd
> like to
> >>>> try booting a kernel :)
> >>>>
> >>>> Thanks,
> >>>> Corey
> >>>>
> >>> I agree with Ron.  You're doing good work and we could help you easier
> if
> >>> we commit it.  I added one more line to your Makefile and it tries to
> build
> >>> the file.
> >>>
> >>> I think the c7.c file should move, but for now it helps.
> >>>
> >>> Thanks,
> >>> Myles
> >>>
> >>>
> >> Ok, adding it there work. But why does it work there but nowhere else?
> I'll
> >> try to make a commit within the hour, I've just got to split the
> c7/cn700
> >> stuff off from the other hacking I've been doing.
> >>
> >>
> >
> > self-acked and committed, feel free to move c7.c anywhere you think it
> > belongs ;) I've self-acked for expediency, I'm about to brave a snowstorm
> to
> > get to school for a final, and won't be back for probably 4 hours or so.
> I
> > also updated the epia-cn dts, so it should be in the same state as the
> j7f2
> > if you fix the superio stuff.
> >
>
> Sorry I didn't find time to review this sooner. Is it intentional that
> one of the files written by you had a (C) coresystems?


Yes - those files are pretty much direct copies from v2 code, just with the
v3 driver struct, x_t -> struct x changes, and include files fixed.

-Corey
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